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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
ARM: rmobile: Remove SD clock configuration from board files
The configuration is now fully performed by the SD and clk drivers, so remove it from the board file. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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2 changed files with 0 additions and 35 deletions
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@ -51,17 +51,8 @@ void s_init(void)
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
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#define ETHERAVB_MSTP812 BIT(12)
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#define DVFS_MSTP926 BIT(26)
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#define SD0_MSTP314 BIT(14)
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#define SD1_MSTP313 BIT(13)
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#define SD2_MSTP312 BIT(12) /* either MMC0 */
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#define SD3_MSTP311 BIT(11) /* either MMC1 */
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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#define SD0CKCR 0xE6150074
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE6150268
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#define SD3CKCR 0xE615026C
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int board_early_init_f(void)
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{
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/* TMU0,1 */ /* which use ? */
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@ -70,15 +61,6 @@ int board_early_init_f(void)
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
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/* EHTERAVB */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
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/* eMMC */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
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/* SDHI0, 3 */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
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writel(1, SD0CKCR);
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writel(1, SD1CKCR);
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writel(1, SD2CKCR);
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writel(1, SD3CKCR);
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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@ -50,16 +50,8 @@ void s_init(void)
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
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#define ETHERAVB_MSTP812 BIT(12)
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#define DVFS_MSTP926 BIT(26)
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#define SD0_MSTP314 BIT(14)
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#define SD1_MSTP313 BIT(13)
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#define SD2_MSTP312 BIT(12) /* either MMC0 */
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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#define SD0CKCR 0xE6150074
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE6150268
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#define SD3CKCR 0xE615026C
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int board_early_init_f(void)
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{
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/* TMU0,1 */ /* which use ? */
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@ -68,15 +60,6 @@ int board_early_init_f(void)
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
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/* EHTERAVB */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
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/* eMMC */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
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/* SDHI0 */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
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writel(1, SD0CKCR);
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writel(1, SD1CKCR);
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writel(1, SD2CKCR);
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writel(1, SD3CKCR);
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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