From 63d0c33622e9e0fc7e512b89de85f88bb8301a60 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Tue, 19 May 2020 23:21:32 +0530 Subject: [PATCH] board: qca: ipq5018: Remove GCC_SDCC1_MISC register. This change will remove GCC_SDCC1_MISC register from SDCC clock configuration code path. Since in ipq5018 this register is not available. so removining this register. Signed-off-by: Md Sadre Alam Change-Id: I980fc0f0ce24cd0da5610300608a5dd223c33941 --- board/qca/arm/ipq5018/ipq5018.c | 18 +++++++++--------- board/qca/arm/ipq5018/ipq5018.h | 4 ---- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index ee1d076528..66c5b1d915 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -259,6 +259,10 @@ void emmc_clock_config(void) /* Delay for clock operation complete */ udelay(10); writel(0x1, GCC_SDCC1_APPS_M); + /* check this M, N D value while debugging + * because as per clock tool the actual M, N, D + * values are M=1, N=FA, D=F9 + */ writel(0xFC, GCC_SDCC1_APPS_N); writel(0xFD, GCC_SDCC1_APPS_D); /* Delay for clock operation complete */ @@ -286,15 +290,12 @@ void sdhci_bus_pwr_off(struct sdhci_host *host) sdhci_writeb(host,(val & (~SDHCI_POWER_ON)), SDHCI_POWER_CONTROL); } -void emmc_clock_disable(void) +__weak void board_mmc_deinit(void) { - /* Clear divider */ - writel(0x0, GCC_SDCC1_MISC); -} - -void board_mmc_deinit(void) -{ - emmc_clock_disable(); + /*since we do not have misc register in ipq5018 + * so simply return from this function + */ + return; } void emmc_clock_reset(void) @@ -325,7 +326,6 @@ int board_mmc_init(bd_t *bis) mmc_host.cfg.part_type = PART_TYPE_EFI; mmc_host.quirks = SDHCI_QUIRK_BROKEN_VOLTAGE; - emmc_clock_disable(); emmc_clock_reset(); udelay(10); emmc_clock_config(); diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index 07ffc09be7..00ecbc3e66 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -99,7 +99,6 @@ #define GCC_SDCC1_APPS_D 0x01842014 #define GCC_SDCC1_APPS_CBCR 0x01842018 #define GCC_SDCC1_AHB_CBCR 0x0184201C -#define GCC_SDCC1_MISC 0x01842020 /* * GCC-QPIC Registers @@ -142,9 +141,6 @@ #define GCC_BLSP1_UART2_APPS_N 0x01803040 #define GCC_BLSP1_UART2_APPS_D 0x01803044 - -#define GCC_SDCC1_BCR 0x01842000 - #define GCC_UART_CFG_RCGR_MODE_MASK 0x3000 #define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700 #define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F