diff --git a/arch/arm/dts/ipq806x-soc.dtsi b/arch/arm/dts/ipq806x-soc.dtsi index 45d0cece4f..1ab7af3fed 100644 --- a/arch/arm/dts/ipq806x-soc.dtsi +++ b/arch/arm/dts/ipq806x-soc.dtsi @@ -19,8 +19,11 @@ compatible = "qca,ipq-uartdm"; reg = <0x16340000 0x200>; gsbi_base = <0x16300000>; - id = <2>; + id = <4>; bit_rate = <0xCC>; + m_value = <0x0C>; + n_value = <0x271>; + d_value = <0x139>; }; timer { diff --git a/arch/arm/include/asm/arch-qcom-common/uart.h b/arch/arm/include/asm/arch-qcom-common/uart.h index 54e38ae39a..79238dd0db 100644 --- a/arch/arm/include/asm/arch-qcom-common/uart.h +++ b/arch/arm/include/asm/arch-qcom-common/uart.h @@ -78,6 +78,18 @@ enum MSM_BOOT_UART_DM_BITS_PER_CHAR { MSM_BOOT_UART_DM_8_BPS }; +/* Information about a serial port */ +struct ipq_serial_platdata { + + unsigned long reg_base; /* address of registers in physical memory */ + u8 port_id; /* uart port number */ + u8 bit_rate; + int m_value; + int n_value; + int d_value; + +}; + /* UART clock @ 7.3728 MHz */ #ifdef CONFIG_IPQ806X #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC @@ -90,7 +102,6 @@ enum MSM_BOOT_UART_DM_BITS_PER_CHAR { (MSM_BOOT_UART_DM_SBL_1 << 2) | \ (MSM_BOOT_UART_DM_8_BPS << 4)) -#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c /* UART_DM Registers */ /* UART Operational Mode Register */ diff --git a/board/qca/ipq40xx/ipq40xx.c b/board/qca/ipq40xx/ipq40xx.c index b3f9d51a1a..b9828f7982 100644 --- a/board/qca/ipq40xx/ipq40xx.c +++ b/board/qca/ipq40xx/ipq40xx.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -289,6 +290,12 @@ int board_late_init(void) return 0; } +void qca_serial_init(struct ipq_serial_platdata *plat) +{ + qca_configure_gpio(gboard_param->console_uart_cfg->dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); + writel(1, GCC_BLSP1_UART1_APPS_CBCR); +} /* * This function is called in the very beginning. * Retreive the machtype info from SMEM and map the board specific diff --git a/board/qca/ipq40xx/ipq40xx.h b/board/qca/ipq40xx/ipq40xx.h index 2f38a540a9..a262c16c53 100644 --- a/board/qca/ipq40xx/ipq40xx.h +++ b/board/qca/ipq40xx/ipq40xx.h @@ -25,7 +25,7 @@ #define NO_OF_I2C_GPIOS 2 #endif #define MAX_CONF_NAME 5 - +#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c unsigned int smem_get_board_machtype(void); extern qca_mmc mmc_host; @@ -139,5 +139,4 @@ typedef enum { extern board_ipq40xx_params_t *gboard_param; unsigned int get_board_index(unsigned int machid); void qca_configure_gpio(gpio_func_data_t *gpio, uint count); - #endif diff --git a/board/qca/ipq806x/ipq806x.c b/board/qca/ipq806x/ipq806x.c index 7eb6b37091..fd8ab59e28 100644 --- a/board/qca/ipq806x/ipq806x.c +++ b/board/qca/ipq806x/ipq806x.c @@ -15,12 +15,33 @@ #include #include #include - +#include +#include +#include #include "ipq806x.h" #include "../common/qca_common.h" DECLARE_GLOBAL_DATA_PTR; +gpio_func_data_t gsbi4_gpio[] = { + + { + .gpio = 10, + .func = 1, + .pull = GPIO_NO_PULL, + .drvstr = GPIO_12MA, + .oe = GPIO_OE_ENABLE + }, + + { + .gpio = 11, + .func = 1, + .pull = GPIO_NO_PULL, + .drvstr = GPIO_12MA, + .oe = GPIO_OE_ENABLE + }, +}; + qca_mmc mmc_host; void enable_caches(void) @@ -71,3 +92,27 @@ int board_mmc_init(bd_t *bis) return ret; } +void ipq_configure_gpio(gpio_func_data_t *gpio, uint count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_tlmm_config(gpio->gpio, gpio->func, gpio->out, + gpio->pull, gpio->drvstr, gpio->oe); + gpio++; + } +} + +void qca_serial_init(struct ipq_serial_platdata *plat) +{ + ipq_configure_gpio(gsbi4_gpio, 2); + writel(GSBI_PROTOCOL_CODE_I2C_UART << + GSBI_CTRL_REG_PROTOCOL_CODE_S, + GSBI_CTRL_REG(GSBI4_BASE)); + + if(!(plat->m_value == -1) || ( plat->n_value == -1) || (plat->d_value == -1)) + uart_clock_config(plat->port_id, + plat->m_value, + plat->n_value, + plat->d_value); +} diff --git a/board/qca/ipq806x/ipq806x.h b/board/qca/ipq806x/ipq806x.h index ca76a5ef4f..da923a7796 100644 --- a/board/qca/ipq806x/ipq806x.h +++ b/board/qca/ipq806x/ipq806x.h @@ -17,4 +17,15 @@ #include #include +typedef struct { + int gpio; + unsigned int func; + unsigned int out; + unsigned int pull; + unsigned int drvstr; + unsigned int oe; +} gpio_func_data_t; + +#define GSBI4_BASE 0x16300000 +void ipq_configure_gpio(gpio_func_data_t *gpio, uint count); #endif /* _IPQ806X_H_ */ diff --git a/board/qca/ipq807x/ipq807x.c b/board/qca/ipq807x/ipq807x.c index 3b0bec8ee3..7a9cf5657a 100644 --- a/board/qca/ipq807x/ipq807x.c +++ b/board/qca/ipq807x/ipq807x.c @@ -19,6 +19,7 @@ #include "ipq807x.h" #include #include +#include #include @@ -36,12 +37,16 @@ void disable_caches(void) icache_disable(); } - int board_init(void) { return 0; } +void qca_serial_init(struct ipq_serial_platdata *plat) +{ + writel(1, GCC_BLSP1_UART1_APPS_CBCR); +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/board/qca/ipq807x/ipq807x.h b/board/qca/ipq807x/ipq807x.h index 3a8782d758..305f3f2551 100644 --- a/board/qca/ipq807x/ipq807x.h +++ b/board/qca/ipq807x/ipq807x.h @@ -27,6 +27,7 @@ #define GCC_SDCC1_APPS_M 0x184200C #define GCC_SDCC1_APPS_N 0x1842010 #define GCC_SDCC1_APPS_D 0x1842014 +#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c typedef enum { SMEM_SPINLOCK_ARRAY = 7, diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 40459ecc6c..b8cc879cc6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -9,6 +9,7 @@ ccflags-y += -I$(srctree)/board/qca/ipq40xx cppflags-y += -I$(srctree)/board/qca/ipq40xx obj-$(CONFIG_ARCH_IPQ807x) += qcom_uart.o +obj-$(CONFIG_ARCH_IPQ806x) += qcom_uart.o obj-$(CONFIG_ARCH_IPQ40xx) += qcom_uart.o ifdef CONFIG_DM_SERIAL obj-y += serial-uclass.o diff --git a/drivers/serial/qcom_uart.c b/drivers/serial/qcom_uart.c index ec5c8b028c..0e6c071118 100644 --- a/drivers/serial/qcom_uart.c +++ b/drivers/serial/qcom_uart.c @@ -36,7 +36,6 @@ #include #include #include - #include #include #include @@ -44,19 +43,8 @@ #include #include -#ifdef CONFIG_ARCH_IPQ40xx -#include "ipq40xx.h" -extern board_ipq40xx_params_t *gboard_param; -#endif - DECLARE_GLOBAL_DATA_PTR; -/* Information about a serial port */ -struct ipq_serial_platdata { - unsigned long reg_base; /* address of registers in physical memory */ - u8 port_id; /* uart port number */ - u8 bit_rate; -}; #define FIFO_DATA_SIZE 4 @@ -356,13 +344,8 @@ static unsigned int msm_boot_uart_dm_init(unsigned long uart_dm_base) static void ipq_serial_init(struct ipq_serial_platdata *plat, unsigned long base) { - -#ifdef CONFIG_ARCH_IPQ40xx - qca_configure_gpio(gboard_param->console_uart_cfg->dbg_uart_gpio, - NO_OF_DBG_UART_GPIOS); -#endif - writel(1, GCC_BLSP1_UART1_APPS_CBCR); - writel(plat->bit_rate, MSM_BOOT_UART_DM_CSR(base)); + qca_serial_init(plat); + writel(plat->bit_rate, MSM_BOOT_UART_DM_CSR(base)); /* Intialize UART_DM */ msm_boot_uart_dm_init(base); @@ -449,6 +432,9 @@ static int ipq_serial_ofdata_to_platdata(struct udevice *dev) plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1); plat->bit_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bit_rate", -1); + plat->m_value = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "m_value", -1); + plat->n_value = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "n_value", -1); + plat->d_value = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "d_value", -1); return 0; }