mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 00:41:17 +01:00
driver: net: qca8084: reduce clk identifier string size
This size of clock identifier string is large, so which in-turn reflects in the size of the qca8084_clk object file, and thus increase uboot size. By reducing the clk identifier string size, we can save around 0.9K. Change-Id: Ic986155b6cc2692d67e9c855928ce8039d294d3f Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This commit is contained in:
Ram Kumar D
parent
75bc424247
commit
5fa35de070
1 changed files with 66 additions and 66 deletions
|
|
@ -13,88 +13,88 @@
|
|||
#ifndef _QCA8084_CLK_H_
|
||||
#define _QCA8084_CLK_H_
|
||||
|
||||
#define QCA8084_SWITCH_CORE_CLK "qca8084_gcc_switch_core_clk"
|
||||
#define QCA8084_APB_BRIDGE_CLK "qca8084_gcc_apb_bridge_clk"
|
||||
#define QCA8084_SWITCH_CORE_CLK "switch_clk"
|
||||
#define QCA8084_APB_BRIDGE_CLK "apb_clk"
|
||||
|
||||
#define QCA8084_MAC0_TX_CLK "qca8084_gcc_mac0_tx_clk"
|
||||
#define QCA8084_MAC0_TX_UNIPHY1_CLK "qca8084_gcc_mac0_tx_srds1_clk"
|
||||
#define QCA8084_MAC0_TX_CLK "m0_tx_clk"
|
||||
#define QCA8084_MAC0_TX_UNIPHY1_CLK "m0_tx_srds1_clk"
|
||||
|
||||
#define QCA8084_MAC0_RX_CLK "qca8084_gcc_mac0_rx_clk"
|
||||
#define QCA8084_MAC0_RX_UNIPHY1_CLK "qca8084_gcc_mac0_rx_srds1_clk"
|
||||
#define QCA8084_MAC0_RX_CLK "m0_rx_clk"
|
||||
#define QCA8084_MAC0_RX_UNIPHY1_CLK "m0_rx_srds1_clk"
|
||||
|
||||
#define QCA8084_MAC1_TX_CLK "qca8084_gcc_mac1_tx_clk"
|
||||
#define QCA8084_MAC1_GEPHY0_TX_CLK "qca8084_gcc_mac1_gephy0_tx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_RX_CLK "qca8084_gcc_mac1_srds1_ch0_rx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK "qca8084_gcc_mac1_srds1_ch0_xgmii_rx_clk"
|
||||
#define QCA8084_MAC1_TX_CLK "m1_tx_clk"
|
||||
#define QCA8084_MAC1_GEPHY0_TX_CLK "m1_gp0_tx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_RX_CLK "m1_srds1_ch0_rx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK "m1_srds1_ch0_xgmii_rx_clk"
|
||||
|
||||
#define QCA8084_MAC1_RX_CLK "qca8084_gcc_mac1_rx_clk"
|
||||
#define QCA8084_MAC1_GEPHY0_RX_CLK "qca8084_gcc_mac1_gephy0_rx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_TX_CLK "qca8084_gcc_mac1_srds1_ch0_tx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK "qca8084_gcc_mac1_srds1_ch0_xgmii_tx_clk"
|
||||
#define QCA8084_MAC1_RX_CLK "m1_rx_clk"
|
||||
#define QCA8084_MAC1_GEPHY0_RX_CLK "m1_gp0_rx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_TX_CLK "m1_srds1_ch0_tx_clk"
|
||||
#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK "m1_srds1_ch0_xgmii_tx_clk"
|
||||
|
||||
#define QCA8084_MAC2_TX_CLK "qca8084_gcc_mac2_tx_clk"
|
||||
#define QCA8084_MAC2_GEPHY1_TX_CLK "qca8084_gcc_mac2_gephy1_tx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_RX_CLK "qca8084_gcc_mac2_srds1_ch1_rx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK "qca8084_gcc_mac2_srds1_ch1_xgmii_rx_clk"
|
||||
#define QCA8084_MAC2_TX_CLK "m2_tx_clk"
|
||||
#define QCA8084_MAC2_GEPHY1_TX_CLK "m2_gp1_tx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_RX_CLK "m2_srds1_ch1_rx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK "m2_srds1_ch1_xgmii_rx_clk"
|
||||
|
||||
#define QCA8084_MAC2_RX_CLK "qca8084_gcc_mac2_rx_clk"
|
||||
#define QCA8084_MAC2_GEPHY1_RX_CLK "qca8084_gcc_mac2_gephy1_rx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_TX_CLK "qca8084_gcc_mac2_srds1_ch1_tx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK "qca8084_gcc_mac2_srds1_ch1_xgmii_tx_clk"
|
||||
#define QCA8084_MAC2_RX_CLK "m2_rx_clk"
|
||||
#define QCA8084_MAC2_GEPHY1_RX_CLK "m2_gp1_rx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_TX_CLK "m2_srds1_ch1_tx_clk"
|
||||
#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK "m2_srds1_ch1_xgmii_tx_clk"
|
||||
|
||||
#define QCA8084_MAC3_TX_CLK "qca8084_gcc_mac3_tx_clk"
|
||||
#define QCA8084_MAC3_GEPHY2_TX_CLK "qca8084_gcc_mac3_gephy2_tx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_RX_CLK "qca8084_gcc_mac3_srds1_ch2_rx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK "qca8084_gcc_mac3_srds1_ch2_xgmii_rx_clk"
|
||||
#define QCA8084_MAC3_TX_CLK "m3_tx_clk"
|
||||
#define QCA8084_MAC3_GEPHY2_TX_CLK "m3_gp2_tx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_RX_CLK "m3_srds1_ch2_rx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK "m3_srds1_ch2_xgmii_rx_clk"
|
||||
|
||||
#define QCA8084_MAC3_RX_CLK "qca8084_gcc_mac3_rx_clk"
|
||||
#define QCA8084_MAC3_GEPHY2_RX_CLK "qca8084_gcc_mac3_gephy2_rx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_TX_CLK "qca8084_gcc_mac3_srds1_ch2_tx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK "qca8084_gcc_mac3_srds1_ch2_xgmii_tx_clk"
|
||||
#define QCA8084_MAC3_RX_CLK "m3_rx_clk"
|
||||
#define QCA8084_MAC3_GEPHY2_RX_CLK "m3_gp2_rx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_TX_CLK "m3_srds1_ch2_tx_clk"
|
||||
#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK "m3_srds1_ch2_xgmii_tx_clk"
|
||||
|
||||
#define QCA8084_MAC4_TX_CLK "qca8084_gcc_mac4_tx_clk"
|
||||
#define QCA8084_MAC4_GEPHY3_TX_CLK "qca8084_gcc_mac4_gephy3_tx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_RX_CLK "qca8084_gcc_mac4_srds1_ch3_rx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK "qca8084_gcc_mac4_srds1_ch3_xgmii_rx_clk"
|
||||
#define QCA8084_MAC4_TX_CLK "m4_tx_clk"
|
||||
#define QCA8084_MAC4_GEPHY3_TX_CLK "m4_gp3_tx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_RX_CLK "m4_srds1_ch3_rx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK "m4_srds1_ch3_xgmii_rx_clk"
|
||||
|
||||
#define QCA8084_MAC4_RX_CLK "qca8084_gcc_mac4_rx_clk"
|
||||
#define QCA8084_MAC4_GEPHY3_RX_CLK "qca8084_gcc_mac4_gephy3_rx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_TX_CLK "qca8084_gcc_mac4_srds1_ch3_tx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK "qca8084_gcc_mac4_srds1_ch3_xgmii_tx_clk"
|
||||
#define QCA8084_MAC4_RX_CLK "m4_rx_clk"
|
||||
#define QCA8084_MAC4_GEPHY3_RX_CLK "m4_gp3_rx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_TX_CLK "m4_srds1_ch3_tx_clk"
|
||||
#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK "m4_srds1_ch3_xgmii_tx_clk"
|
||||
|
||||
#define QCA8084_MAC5_TX_CLK "qca8084_gcc_mac5_tx_clk"
|
||||
#define QCA8084_MAC5_TX_UNIPHY0_CLK "qca8084_gcc_mac5_tx_srds0_clk"
|
||||
#define QCA8084_MAC5_TX_SRDS0_CLK_SRC "qca8084_gcc_mac5_tx_srds0_clk_src"
|
||||
#define QCA8084_MAC5_TX_CLK "m5_tx_clk"
|
||||
#define QCA8084_MAC5_TX_UNIPHY0_CLK "m5_tx_srds0_clk"
|
||||
#define QCA8084_MAC5_TX_SRDS0_CLK_SRC "m5_tx_srds0_clk_src"
|
||||
|
||||
#define QCA8084_MAC5_RX_CLK "qca8084_gcc_mac5_rx_clk"
|
||||
#define QCA8084_MAC5_RX_UNIPHY0_CLK "qca8084_gcc_mac5_rx_srds0_clk"
|
||||
#define QCA8084_MAC5_RX_SRDS0_CLK_SRC "qca8084_gcc_mac5_rx_srds0_clk_src"
|
||||
#define QCA8084_MAC5_RX_CLK "m5_rx_clk"
|
||||
#define QCA8084_MAC5_RX_UNIPHY0_CLK "m5_rx_srds0_clk"
|
||||
#define QCA8084_MAC5_RX_SRDS0_CLK_SRC "m5_rx_srds0_clk_src"
|
||||
|
||||
#define QCA8084_SEC_CTRL_CLK "qca8084_gcc_sec_ctrl_clk"
|
||||
#define QCA8084_SEC_CTRL_SENSE_CLK "qca8084_gcc_sec_ctrl_sense_clk"
|
||||
#define QCA8084_SEC_CTRL_CLK "sec_ctrl_clk"
|
||||
#define QCA8084_SEC_CTRL_SENSE_CLK "sec_ctrl_sense_clk"
|
||||
|
||||
#define QCA8084_SRDS0_SYS_CLK "qca8084_gcc_srds0_sys_clk"
|
||||
#define QCA8084_SRDS1_SYS_CLK "qca8084_gcc_srds1_sys_clk"
|
||||
#define QCA8084_GEPHY0_SYS_CLK "qca8084_gcc_gephy0_sys_clk"
|
||||
#define QCA8084_GEPHY1_SYS_CLK "qca8084_gcc_gephy1_sys_clk"
|
||||
#define QCA8084_GEPHY2_SYS_CLK "qca8084_gcc_gephy2_sys_clk"
|
||||
#define QCA8084_GEPHY3_SYS_CLK "qca8084_gcc_gephy3_sys_clk"
|
||||
#define QCA8084_SRDS0_SYS_CLK "srds0_sys_clk"
|
||||
#define QCA8084_SRDS1_SYS_CLK "srds1_sys_clk"
|
||||
#define QCA8084_GEPHY0_SYS_CLK "gp0_sys_clk"
|
||||
#define QCA8084_GEPHY1_SYS_CLK "gp1_sys_clk"
|
||||
#define QCA8084_GEPHY2_SYS_CLK "gp2_sys_clk"
|
||||
#define QCA8084_GEPHY3_SYS_CLK "gp3_sys_clk"
|
||||
|
||||
#define QCA8084_AHB_CLK "qca8084_gcc_ahb_clk"
|
||||
#define QCA8084_SEC_CTRL_AHB_CLK "qca8084_gcc_sec_ctrl_ahb_clk"
|
||||
#define QCA8084_TLMM_CLK "qca8084_gcc_tlmm_clk"
|
||||
#define QCA8084_TLMM_AHB_CLK "qca8084_gcc_tlmm_ahb_clk"
|
||||
#define QCA8084_CNOC_AHB_CLK "qca8084_gcc_cnoc_ahb_clk"
|
||||
#define QCA8084_MDIO_AHB_CLK "qca8084_gcc_mdio_ahb_clk"
|
||||
#define QCA8084_MDIO_MASTER_AHB_CLK "qca8084_gcc_mdio_master_ahb_clk"
|
||||
#define QCA8084_AHB_CLK "ahb_clk"
|
||||
#define QCA8084_SEC_CTRL_AHB_CLK "sec_ctrl_ahb_clk"
|
||||
#define QCA8084_TLMM_CLK "tlmm_clk"
|
||||
#define QCA8084_TLMM_AHB_CLK "tlmm_ahb_clk"
|
||||
#define QCA8084_CNOC_AHB_CLK "cnoc_ahb_clk"
|
||||
#define QCA8084_MDIO_AHB_CLK "mdio_ahb_clk"
|
||||
#define QCA8084_MDIO_MASTER_AHB_CLK "mdio_master_ahb_clk"
|
||||
|
||||
#define QCA8084_GLOBAL_RST "qca8084_gcc_global_rst"
|
||||
#define QCA8084_UNIPHY_XPCS_RST "qca8084_uniphy_xpcs_rst"
|
||||
#define QCA8084_GEPHY_DSP_HW_RST "qca8084_gephy_dsp_hw_rst"
|
||||
#define QCA8084_GEPHY_P3_MDC_SW_RST "qca8084_gephy_p3_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P2_MDC_SW_RST "qca8084_gephy_p2_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P1_MDC_SW_RST "qca8084_gephy_p1_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P0_MDC_SW_RST "qca8084_gephy_p0_mdc_sw_rst"
|
||||
#define QCA8084_GLOBAL_RST "global_rst"
|
||||
#define QCA8084_UNIPHY_XPCS_RST "xpcs_rst"
|
||||
#define QCA8084_GEPHY_DSP_HW_RST "dsp_hw_rst"
|
||||
#define QCA8084_GEPHY_P3_MDC_SW_RST "p3_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P2_MDC_SW_RST "p2_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P1_MDC_SW_RST "p1_mdc_sw_rst"
|
||||
#define QCA8084_GEPHY_P0_MDC_SW_RST "p0_mdc_sw_rst"
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue