From 5b941d0f314fbcdcf52acf798474bbbf1f990ea0 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Fri, 25 Nov 2022 19:58:53 +0530 Subject: [PATCH] arm: dts: ipq5332: Enable support for USB This patch enables support for USB 2.0 in AP-MI01.2 Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a Signed-off-by: Timple Raj M --- arch/arm/dts/ipq5332-mi01.2.dts | 2 +- arch/arm/include/asm/arch-ipq5332/clk.h | 1 + board/qca/arm/ipq5332/clock.c | 2 +- board/qca/arm/ipq5332/ipq5332.c | 18 ++++++++---------- 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/ipq5332-mi01.2.dts b/arch/arm/dts/ipq5332-mi01.2.dts index ad4eb9c99b..46cfdb476f 100644 --- a/arch/arm/dts/ipq5332-mi01.2.dts +++ b/arch/arm/dts/ipq5332-mi01.2.dts @@ -23,7 +23,7 @@ console = "/serial@78AF000"; nand = "/nand-controller@79B0000"; mmc = "/sdhci@7804000"; - usb0 = "xhci@8a00000"; + usb0 = "/xhci@8a00000"; i2c0 = "/i2c@78B6000"; pci0 = "/pci@20000000"; pci1 = "/pci@18000000"; diff --git a/arch/arm/include/asm/arch-ipq5332/clk.h b/arch/arm/include/asm/arch-ipq5332/clk.h index 23aead20ec..c4ef44253a 100644 --- a/arch/arm/include/asm/arch-ipq5332/clk.h +++ b/arch/arm/include/asm/arch-ipq5332/clk.h @@ -231,6 +231,7 @@ #define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8) #define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0x7 << 0) +#define GCC_USB_MOCK_UTMI_MN_MODE (2 << 12) #define GCC_USB_MOCK_UTMI_SRC_SEL (1 << 8) #define GCC_USB_MOCK_UTMI_SRC_DIV (0x13 << 0) #define MOCK_UTMI_M 0x1 diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c index 2463efe198..0d796eb18e 100644 --- a/board/qca/arm/ipq5332/clock.c +++ b/board/qca/arm/ipq5332/clock.c @@ -277,7 +277,7 @@ void usb_clock_init(void) writel(ROOT_EN, GCC_USB0_MASTER_CMD_RCGR); /* Configure usb0_mock_utmi_clk_src */ - cfg = (GCC_USB_MOCK_UTMI_SRC_SEL | + cfg = (GCC_USB_MOCK_UTMI_MN_MODE | GCC_USB_MOCK_UTMI_SRC_SEL | GCC_USB_MOCK_UTMI_SRC_DIV); writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR); writel(MOCK_UTMI_M, GCC_USB0_MOCK_UTMI_M); diff --git a/board/qca/arm/ipq5332/ipq5332.c b/board/qca/arm/ipq5332/ipq5332.c index 4f1a7651da..8536b4365c 100644 --- a/board/qca/arm/ipq5332/ipq5332.c +++ b/board/qca/arm/ipq5332/ipq5332.c @@ -559,25 +559,23 @@ static void usb_init_hsphy(void __iomem *phybase, int ssphy) writel(FREQ_SEL, phybase + USB_PHY_FSEL_SEL); /* Configure refclk frequency */ - writel(FSEL_VALUE << FSEL, phybase + USB_PHY_HS_PHY_CTRL_COMMON0); + writel(COMMONONN | FSEL_VALUE | RETENABLEN, + phybase + USB_PHY_HS_PHY_CTRL_COMMON0); - writel(readl(phybase + USB_PHY_UTMI_CTRL5) & ATERESET, + writel(POR_EN & ATERESET, phybase + USB_PHY_UTMI_CTRL5); - writel(USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + writel(USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN, phybase + USB_PHY_HS_PHY_CTRL2); - writel(SLEEPM, phybase + USB_PHY_UTMI_CTRL0); - - writel(XCFG_COARSE_TUNE_NUM | XCFG_COARSE_TUNE_NUM, + writel(XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, phybase + USB2PHY_USB_PHY_M31_XCFGI_11); - udelay(100); + udelay(10); - writel(readl(phybase + USB_PHY_UTMI_CTRL5) & ~POR_EN, - phybase + USB_PHY_UTMI_CTRL5); + writel(0, phybase + USB_PHY_UTMI_CTRL5); - writel(readl(phybase + USB_PHY_HS_PHY_CTRL2) & USB2_SUSPEND_N_SEL, + writel(USB2_SUSPEND_N | USB2_UTMI_CLK_EN, phybase + USB_PHY_HS_PHY_CTRL2); }