From 1d89a6f1da5ec7e05de2808437ddc0dfa8c46bfc Mon Sep 17 00:00:00 2001 From: Antony Arun T Date: Mon, 25 Mar 2019 15:29:43 +0530 Subject: [PATCH] ipq6018: configuring SDHC1_AHB_CBCR clock Change-Id: I818e5cc0da74240a78ffeb15a1765be4501f6756 Signed-off-by: Antony Arun T --- board/qca/arm/ipq6018/ipq6018.c | 1 + board/qca/arm/ipq6018/ipq6018.h | 1 + 2 files changed, 2 insertions(+) diff --git a/board/qca/arm/ipq6018/ipq6018.c b/board/qca/arm/ipq6018/ipq6018.c index 4509510bfe..759afdb89c 100644 --- a/board/qca/arm/ipq6018/ipq6018.c +++ b/board/qca/arm/ipq6018/ipq6018.c @@ -146,6 +146,7 @@ void emmc_clock_config() writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR); /* Add 10us delay for CLK_OFF to get cleared */ udelay(10); + writel(readl(GCC_SDCC1_AHB_CBCR)|0x1, GCC_SDCC1_AHB_CBCR); /* PLL0 - 192Mhz */ writel(0x20B, GCC_SDCC1_APPS_CFG_RCGR); /* Delay for clock operation complete */ diff --git a/board/qca/arm/ipq6018/ipq6018.h b/board/qca/arm/ipq6018/ipq6018.h index ca1452084a..c3d346c7af 100644 --- a/board/qca/arm/ipq6018/ipq6018.h +++ b/board/qca/arm/ipq6018/ipq6018.h @@ -30,6 +30,7 @@ #define GCC_SDCC1_APPS_D 0x1842014 #define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c #define GCC_SDCC1_BCR 0x01842000 +#define GCC_SDCC1_AHB_CBCR 0x0184201C #define GCC_BLSP1_UART2_APPS_CFG_RCGR 0x01803038 #define GCC_BLSP1_UART2_APPS_M 0x0180303C