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drivers: net: ipq9574: Update Eth configurations

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This patch updates the following:

1) Removes unnecessary TIMER and THRESHOLD configurations in EDMA
2) Adds Uniphy Clock deinit and init in eth_init (during each ping
& speed change)
3) Removes preheader configurations and calculations from EDMA
as there are no preheaders in ipq9574 platform (Instead there is
a secondary descriptor)
4) Add sufficient delay after uniphy reset
5) Remove CONFIG_IPQ9574_RUMI macro from network drivers
6) Change default mac_speed to 0
7) Fix the ppe sched. and tdm configuration
8) Reduce the block size to 1280 + headers for tftp (around 1326)
for timebeing without which timeouts were observed randomly during
TFTP (Note that the MTU is 1514 bytes)

Change-Id: I4004adfb2ae0dc98d65e458c15dafcff6523744b
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-08-05 18:02:18 +05:30 • committed by Gerrit - the friendly Code Review server
parent f085a51baa
commit 4f92f7e93e
8 changed files with 158 additions and 296 deletions
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64
arch/arm/include/asm/arch-ipq9574/edma_regs.h
View file

@ -47,18 +47,14 @@
#define IPQ9574_EDMA_REG_TXCMPL_PROD_IDX(n) (0x79004 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TXCMPL_CONS_IDX(n) (0x79008 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TXCMPL_RING_SIZE(n) (0x7900c + (0x1000 * n))
#define IPQ9574_EDMA_REG_TXCMPL_UGT_THRE(n) (0x79010 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TXCMPL_CTRL(n) (0x79014 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TX_INT_STAT(n) (0x99000 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TX_INT_MASK(n) (0x99004 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TX_MOD_TIMER(n) (0x99008 + (0x1000 * n))
#define IPQ9574_EDMA_REG_TX_INT_CTRL(n) (0x9900c + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_BA(n) (0x29000 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_PROD_IDX(n) (0x29004 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_CONS_IDX(n) (0x29008 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_RING_SIZE(n) (0x2900c + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_FC_THRE(n) (0x29014 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_UGT_THRE(n) (0x29018 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_RING_EN(n) (0x2901c + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_INT_STAT(n) (0x31000 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXFILL_INT_MASK(n) (0x31004 + (0x1000 * n))
@ -67,12 +63,9 @@
#define IPQ9574_EDMA_REG_RXDESC_PROD_IDX(n) (0x39004 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_CONS_IDX(n) (0x39008 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_RING_SIZE(n) (0x3900c + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_FC_THRE(n) (0x39010 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_UGT_THRE(n) (0x39014 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_CTRL(n) (0x39018 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_INT_STAT(n) (0x59000 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RXDESC_INT_MASK(n) (0x59004 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RX_MOD_TIMER(n) (0x59008 + (0x1000 * n))
#define IPQ9574_EDMA_REG_RX_INT_CTRL(n) (0x5900c + (0x1000 * n))
#define IPQ9574_EDMA_QID2RID_TABLE_MEM(q) (0xb9000 + (0x4 * q))
@ -111,20 +104,6 @@
*/
#define IPQ9574_EDMA_TXCMPL_CONS_IDX_MASK 0xffff
/*
* EDMA_REG_TXCMPL_UGT_THRE register
*/
#define IPQ9574_EDMA_TXCMPL_LOW_THRE_MASK 0xffff
#define IPQ9574_EDMA_TXCMPL_LOW_THRE_SHIFT 0
#define IPQ9574_EDMA_TXCMPL_FC_THRE_MASK 0x3f
#define IPQ9574_EDMA_TXCMPL_FC_THRE_SHIFT 16
/*
* EDMA_REG_TX_MOD_TIMER register
*/
#define IPQ9574_EDMA_TX_MOD_TIMER_INIT_MASK 0xffff
#define IPQ9574_EDMA_TX_MOD_TIMER_INIT_SHIFT 0
/*
* EDMA_REG_TX_INT_CTRL register
*/
@ -147,20 +126,6 @@
#define IPQ9574_EDMA_RXFILL_BUF_SIZE_MASK 0xffff0000
#define IPQ9574_EDMA_RXFILL_BUF_SIZE_SHIFT 16
/*
* EDMA_REG_RXFILL_FC_THRE register
*/
#define IPQ9574_EDMA_RXFILL_FC_XON_THRE_MASK 0x7ff
#define IPQ9574_EDMA_RXFILL_FC_XON_THRE_SHIFT 12
#define IPQ9574_EDMA_RXFILL_FC_XOFF_THRE_MASK 0x7ff
#define IPQ9574_EDMA_RXFILL_FC_XOFF_THRE_SHIFT 0
/*
* EDMA_REG_RXFILL_UGT_THRE register
*/
#define IPQ9574_EDMA_RXFILL_LOW_THRE_MASK 0xffff
#define IPQ9574_EDMA_RXFILL_LOW_THRE_SHIFT 0
/*
* EDMA_REG_RXFILL_RING_EN register
*/
@ -188,20 +153,6 @@
#define IPQ9574_EDMA_RXDESC_PL_OFFSET_MASK 0x1ff
#define IPQ9574_EDMA_RXDESC_PL_OFFSET_SHIFT 16
/*
* EDMA_REG_RXDESC_FC_THRE register
*/
#define IPQ9574_EDMA_RXDESC_FC_XON_THRE_MASK 0x7ff
#define IPQ9574_EDMA_RXDESC_FC_XON_THRE_SHIFT 12
#define IPQ9574_EDMA_RXDESC_FC_XOFF_THRE_MASK 0x7ff
#define IPQ9574_EDMA_RXDESC_FC_XOFF_THRE_SHIFT 0
/*
* EDMA_REG_RXDESC_UGT_THRE register
*/
#define IPQ9574_EDMA_RXDESC_LOW_THRE_MASK 0xffff
#define IPQ9574_EDMA_RXDESC_LOW_THRE_SHIFT 0
/*
* EDMA_REG_RXDESC_CTRL register
*/
@ -219,12 +170,6 @@
#define IPQ9574_EDMA_RXDESC_INT_MASK_PKT_INT 0x1
#define IPQ9574_EDMA_MASK_INT_DISABLE 0x0
/*
* EDMA_REG_RX_MOD_TIMER register
*/
#define IPQ9574_EDMA_RX_MOD_TIMER_INIT_MASK 0xffff
#define IPQ9574_EDMA_RX_MOD_TIMER_INIT_SHIFT 0
/*
* TXDESC shift values
*/
@ -250,13 +195,4 @@
#define IPQ9574_EDMA_TXCMPL_RETMODE_OPAQUE 0x0
#define IPQ9574_EDMA_RXFILL_RING_INT_STATUS_MASK 0x1
/*
* TODO tune the timer and threshold values
*/
#define IPQ9574_EDMA_RXDESC_XON_THRE 50
#define IPQ9574_EDMA_RXDESC_XOFF_THRE 30
#define IPQ9574_EDMA_RXDESC_LOW_THRE 0
#define IPQ9574_EDMA_RX_MOD_TIMER_INIT 1000
#define IPQ9574_EDMA_TX_MOD_TIMER 150
#endif /* __EDMA_REGS__ */

13
board/qca/arm/ipq9574/ipq9574.c
View file

@ -561,7 +561,6 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla
}
#endif
#ifndef CONFIG_IPQ9574_RUMI
int get_aquantia_gpio(int aquantia_gpio[2])
{
int aquantia_gpio_cnt = -1, node;
@ -974,6 +973,14 @@ void uniphy_clk_init(void)
uniphy_clock_enable(i, true);
}
void uniphy_clk_deinit(void)
{
int i;
/* Uniphy clock enable */
for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++)
uniphy_clock_enable(i, false);
}
void cmnblk_init(void)
{
uint32_t gcc_pll_base, reg_val;
@ -1073,16 +1080,12 @@ void ipq9574_eth_initialize(void)
bring_phy_out_of_reset();
}
#endif
#ifdef CONFIG_IPQ9574_EDMA
int board_eth_init(bd_t *bis)
{
int ret = 0;
#ifndef CONFIG_IPQ9574_RUMI
ipq9574_eth_initialize();
#endif
ret = ipq9574_edma_init(NULL);
if (ret != 0)

6
drivers/net/Makefile
View file

@ -87,13 +87,7 @@ obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_edma.o
obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_ppe.o
obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_uniphy.o
obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_ppe.o
ifndef CONFIG_IPQ9574_RUMI
obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_uniphy.o
endif
obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_edma.o
obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_gmac.o
obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_uniphy.o

159
drivers/net/ipq9574/ipq9574_edma.c
View file

@ -49,7 +49,7 @@ uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0};
int sgmii_mode[2] = {0};
#ifndef CONFIG_IPQ9574_RUMI
extern void uniphy_clk_deinit(void);
extern int ipq_sw_mdio_init(const char *);
extern int ipq_mdio_read(int mii_id, int regnum, ushort *data);
extern void ipq9574_qca8075_phy_map_ops(struct phy_ops **ops);
@ -59,7 +59,6 @@ extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_board_fw_download(unsigned int phy_addr);
#endif
static int tftp_acl_our_port;
@ -301,11 +300,6 @@ uint32_t ipq9574_edma_clean_rx(struct ipq9574_edma_common_info *c_info,
cleaned_count++;
/*
* Remove Rx Secondary Descriptor
*/
skb = skb + IPQ9574_EDMA_RX_SEC_DESC_SIZE;
pr_debug("%s: received pkt %p with length %d\n",
__func__, skb, pkt_length);
@ -483,17 +477,13 @@ static int ipq9574_eth_snd(struct eth_device *dev, void *packet, int length)
/*
* copy the packet
*
*/
memcpy(skb + IPQ9574_EDMA_TX_SEC_DESC_SIZE, packet, length);
memcpy(skb, packet, length);
/*
* Populate Tx descriptor
*/
txdesc->tdes6 |= (1 << IPQ9574_EDMA_TXDESC_PREHEADER_SHIFT) |
((IPQ9574_EDMA_TX_SEC_DESC_SIZE <<
IPQ9574_EDMA_TXDESC_DATA_OFFSET_SHIFT) &
IPQ9574_EDMA_TXDESC_DATA_OFFSET_MASK);
txdesc->tdes6 |= (1 << IPQ9574_EDMA_TXDESC_PREHEADER_SHIFT);
txdesc->tdes5 |= ((length << IPQ9574_EDMA_TXDESC_DATA_LENGTH_SHIFT) &
IPQ9574_EDMA_TXDESC_DATA_LENGTH_MASK);
@ -629,8 +619,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
rxfill_ring->count = EDMA_RING_SIZE;
rxfill_ring->id = ehw->rxfill_ring_start + i;
rxfill_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_rxfill_desc) *
rxfill_ring->count,
IPQ9574_EDMA_RXFILL_DESC_SIZE * rxfill_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (rxfill_ring->desc == NULL) {
@ -642,7 +631,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
rxfill_ring->id, rxfill_ring->desc, (unsigned int)
rxfill_ring->dma);
rx_buf = (void *)noncached_alloc(PKTSIZE_ALIGN *
rx_buf = (void *)noncached_alloc(IPQ9574_EDMA_RX_BUFF_SIZE *
rxfill_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
@ -658,7 +647,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
rxfill_desc->rdes1 = 0;
rxfill_desc->rdes2 = 0;
rxfill_desc->rdes3 = 0;
rx_buf += PKTSIZE_ALIGN;
rx_buf += IPQ9574_EDMA_RX_BUFF_SIZE;
pr_debug("Ring %d: rxfill ring dis0 ptr = %p, rxfill ring dis0 dma = %u\n",
j, rxfill_desc, (unsigned int)rxfill_desc->rdes0);
}
@ -672,8 +661,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
sec_rxdesc_ring->count = EDMA_RING_SIZE;
sec_rxdesc_ring->id = ehw->sec_rxdesc_ring_start + i;
sec_rxdesc_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_rx_sec_desc) *
sec_rxdesc_ring->count,
IPQ9574_EDMA_RX_SEC_DESC_SIZE * sec_rxdesc_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (sec_rxdesc_ring->desc == NULL) {
pr_info("%s: sec_rxdesc_ring->desc alloc error\n", __func__);
@ -705,8 +693,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
rxdesc_ring->rxfill = ehw->rxfill_ring;
rxdesc_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_rxdesc_desc) *
rxdesc_ring->count,
IPQ9574_EDMA_RXDESC_DESC_SIZE * rxdesc_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (rxdesc_ring->desc == NULL) {
@ -727,8 +714,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
txcmpl_ring->count = EDMA_RING_SIZE;
txcmpl_ring->id = ehw->txcmpl_ring_start + i;
txcmpl_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_txcmpl_desc) *
txcmpl_ring->count,
IPQ9574_EDMA_TXCMPL_DESC_SIZE * txcmpl_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (txcmpl_ring->desc == NULL) {
@ -749,8 +735,7 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
sec_txdesc_ring->count = EDMA_RING_SIZE;
sec_txdesc_ring->id = ehw->sec_txdesc_ring_start + i;
sec_txdesc_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_tx_sec_desc) *
sec_txdesc_ring->count,
IPQ9574_EDMA_TX_SEC_DESC_SIZE * sec_txdesc_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (sec_txdesc_ring->desc == NULL) {
pr_info("%s: sec_txdesc_ring->desc alloc error\n", __func__);
@ -770,9 +755,8 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
txdesc_ring->count = EDMA_RING_SIZE;
txdesc_ring->id = ehw->txdesc_ring_start + i;
txdesc_ring->desc = (void *)noncached_alloc(
sizeof(struct ipq9574_edma_txdesc_desc) *
txdesc_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
IPQ9574_EDMA_TXDESC_DESC_SIZE * txdesc_ring->count,
CONFIG_SYS_CACHELINE_SIZE);
if (txdesc_ring->desc == NULL) {
pr_info("%s: txdesc_ring->desc alloc error\n", __func__);
return -ENOMEM;
@ -928,7 +912,6 @@ static void ipq9574_edma_disable_intr(struct ipq9574_edma_hw *ehw)
IPQ9574_EDMA_MASK_INT_DISABLE);
}
#ifndef CONFIG_IPQ9574_RUMI
static void set_sgmii_mode(int port_id, int sg_mode)
{
if (port_id == 4)
@ -946,14 +929,12 @@ static int get_sgmii_mode(int port_id)
else
return -1;
}
#endif
static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
{
int i;
u8 status = 0;
int mac_speed = 0x2;
#ifndef CONFIG_IPQ9574_RUMI
int mac_speed = 0x0;
struct ipq9574_eth_dev *priv = eth_dev->priv;
struct phy_ops *phy_get_ops;
static fal_port_speed_t old_speed[IPQ9574_PHY_MAX] = {[0 ... IPQ9574_PHY_MAX-1] = FAL_SPEED_BUTT};
@ -981,14 +962,12 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
}
phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
#endif
/*
* Check PHY link, speed, Duplex on all phys.
* we will proceed even if single link is up
* else we will return with -1;
*/
for (i = 0; i < IPQ9574_PHY_MAX; i++) {
#ifndef CONFIG_IPQ9574_RUMI
if (!priv->ops[i]) {
printf("Phy ops not mapped\n");
continue;
@ -1212,25 +1191,24 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
}
}
uniphy_clk_deinit();
mdelay(150);
ipq9574_speed_clock_set(i, clk);
ipq9574_port_mac_clock_reset(i);
if (i == aquantia_port[0] || i == aquantia_port[1])
ipq9574_uxsgmii_speed_set(i, mac_speed, duplex, status);
else
ipq9574_pqsgmii_speed_set(i, mac_speed, status);
#else
ppe_port_bridge_txmac_set(i + 1, 1);
ipq9574_pqsgmii_speed_set(i, mac_speed, status);
#endif
}
#ifndef CONFIG_IPQ9574_RUMI
if (linkup <= 0) {
/* No PHY link is alive */
return -1;
}
#endif
pr_info("%s: done\n", __func__);
@ -1438,19 +1416,16 @@ static void ipq9574_edma_configure_txdesc_ring(struct ipq9574_edma_hw *ehw,
static void ipq9574_edma_configure_txcmpl_ring(struct ipq9574_edma_hw *ehw,
struct ipq9574_edma_txcmpl_ring *txcmpl_ring)
{
uint32_t txcmpl_ugt_thre, low_thre = 0, txcmpl_fc_thre = 0;
__maybe_unused uint32_t tx_mod_timer;
/*
* Configure TxCmpl ring base address
*/
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_BA(txcmpl_ring->id),
(uint32_t)(txcmpl_ring->dma &
IPQ9574_EDMA_RING_DMA_MASK));
IPQ9574_EDMA_RING_DMA_MASK));
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_RING_SIZE(
txcmpl_ring->id), (uint32_t)(txcmpl_ring->count &
IPQ9574_EDMA_TXDESC_RING_SIZE_MASK));
IPQ9574_EDMA_TXDESC_RING_SIZE_MASK));
/*
* Set TxCmpl ret mode to opaque
@ -1458,28 +1433,11 @@ static void ipq9574_edma_configure_txcmpl_ring(struct ipq9574_edma_hw *ehw,
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id),
IPQ9574_EDMA_TXCMPL_RETMODE_OPAQUE);
txcmpl_ugt_thre = (low_thre & IPQ9574_EDMA_TXCMPL_LOW_THRE_MASK) <<
IPQ9574_EDMA_TXCMPL_LOW_THRE_SHIFT;
txcmpl_ugt_thre |= (txcmpl_fc_thre & IPQ9574_EDMA_TXCMPL_FC_THRE_MASK)
<< IPQ9574_EDMA_TXCMPL_FC_THRE_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_UGT_THRE(
txcmpl_ring->id), txcmpl_ugt_thre);
#ifndef CONFIG_IPQ9574_RUMI
tx_mod_timer = (IPQ9574_EDMA_TX_MOD_TIMER &
IPQ9574_EDMA_TX_MOD_TIMER_INIT_MASK) <<
IPQ9574_EDMA_TX_MOD_TIMER_INIT_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id),
tx_mod_timer);
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_INT_CTRL(txcmpl_ring->id),
0x2);
#endif
0x2);
}
/*
* ipq9574_edma_configure_sec_rxdesc_ring()
* Configure one secondary RxDesc ring
@ -1504,45 +1462,17 @@ static void ipq9574_edma_configure_rxdesc_ring(struct ipq9574_edma_hw *ehw,
(uint32_t)(rxdesc_ring->dma & 0xffffffff));
data = rxdesc_ring->count & IPQ9574_EDMA_RXDESC_RING_SIZE_MASK;
data |= (ehw->rx_payload_offset &
IPQ9574_EDMA_RXDESC_PL_OFFSET_MASK) <<
IPQ9574_EDMA_RXDESC_PL_OFFSET_SHIFT;
data |= (ehw->rx_payload_offset & IPQ9574_EDMA_RXDESC_PL_OFFSET_MASK) <<
IPQ9574_EDMA_RXDESC_PL_OFFSET_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_RING_SIZE(
rxdesc_ring->id), data);
data = (IPQ9574_EDMA_RXDESC_XON_THRE &
IPQ9574_EDMA_RXDESC_FC_XON_THRE_MASK) <<
IPQ9574_EDMA_RXDESC_FC_XON_THRE_SHIFT;
data |= (IPQ9574_EDMA_RXDESC_XOFF_THRE &
IPQ9574_EDMA_RXDESC_FC_XOFF_THRE_MASK) <<
IPQ9574_EDMA_RXDESC_FC_XOFF_THRE_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_FC_THRE(
rxdesc_ring->id), data);
data = (IPQ9574_EDMA_RXDESC_LOW_THRE &
IPQ9574_EDMA_RXDESC_LOW_THRE_MASK) <<
IPQ9574_EDMA_RXDESC_LOW_THRE_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_UGT_THRE(
rxdesc_ring->id), data);
#ifndef CONFIG_IPQ9574_RUMI
data = (IPQ9574_EDMA_RX_MOD_TIMER_INIT &
IPQ9574_EDMA_RX_MOD_TIMER_INIT_MASK) <<
IPQ9574_EDMA_RX_MOD_TIMER_INIT_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RX_MOD_TIMER(
rxdesc_ring->id), data);
rxdesc_ring->id), data);
/*
* Enable ring. Set ret mode to 'opaque'.
*/
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RX_INT_CTRL(
rxdesc_ring->id), 0x2);
#endif
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RX_INT_CTRL(rxdesc_ring->id),
0x2);
}
/*
@ -1552,11 +1482,6 @@ static void ipq9574_edma_configure_rxdesc_ring(struct ipq9574_edma_hw *ehw,
static void ipq9574_edma_configure_rxfill_ring(struct ipq9574_edma_hw *ehw,
struct ipq9574_edma_rxfill_ring *rxfill_ring)
{
uint32_t rxfill_low_thre = (rxfill_ring->count / 4);
uint32_t rxfill_xon_thre = (rxfill_ring->count / 8);
uint32_t rxfill_xoff_thre = (rxfill_ring->count / 16);
uint32_t rxfill_fc_thre;
uint32_t rxfill_ugt_thre;
uint32_t data;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_BA(rxfill_ring->id),
@ -1565,20 +1490,6 @@ static void ipq9574_edma_configure_rxfill_ring(struct ipq9574_edma_hw *ehw,
data = rxfill_ring->count & IPQ9574_EDMA_RXFILL_RING_SIZE_MASK;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data);
rxfill_fc_thre = (rxfill_xon_thre & IPQ9574_EDMA_RXFILL_FC_XON_THRE_MASK)
<< IPQ9574_EDMA_RXFILL_FC_XON_THRE_SHIFT;
rxfill_fc_thre |= (rxfill_xoff_thre & IPQ9574_EDMA_RXFILL_FC_XOFF_THRE_MASK)
<< IPQ9574_EDMA_RXFILL_FC_XOFF_THRE_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_FC_THRE(rxfill_ring->id),
rxfill_fc_thre);
rxfill_ugt_thre = (rxfill_low_thre & IPQ9574_EDMA_RXFILL_LOW_THRE_MASK)
<< IPQ9574_EDMA_RXFILL_LOW_THRE_SHIFT;
ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_UGT_THRE(rxfill_ring->id),
rxfill_ugt_thre);
}
@ -1636,9 +1547,9 @@ static void ipq9574_edma_configure_rings(struct ipq9574_edma_hw *ehw)
void ipq9574_edma_hw_reset(void)
{
writel(NSS_CC_EDMA_HW_RESET_ASSERT, NSS_CC_PPE_RESET_ADDR);
udelay(100);
mdelay(500);
writel(NSS_CC_EDMA_HW_RESET_DEASSERT, NSS_CC_PPE_RESET_ADDR);
udelay(100);
mdelay(100);
}
/*
@ -1666,14 +1577,12 @@ int ipq9574_edma_hw_init(struct ipq9574_edma_hw *ehw)
ehw->txcmpl_intr_mask = IPQ9574_EDMA_TX_INT_MASK_PKT_INT |
IPQ9574_EDMA_TX_INT_MASK_UGT_INT;
ehw->misc_intr_mask = 0xff;
ehw->rx_payload_offset = IPQ9574_EDMA_RX_SEC_DESC_SIZE;
ehw->rx_payload_offset = 0x0;
#ifndef CONFIG_IPQ9574_RUMI
/*
* Reset EDMA
*/
ipq9574_edma_hw_reset();
#endif
/*
* Disable interrupts
@ -1762,7 +1671,7 @@ int ipq9574_edma_hw_init(struct ipq9574_edma_hw *ehw)
/*
* Set PPE QID to EDMA Rx ring mapping.
* When coming up use only queue 0.
* HOST EDMA rings. FW EDMA comes up and overwrites as required.
* HOST EDMA rings.
* Each entry can hold mapping for 8 PPE queues and entry size is
* 4 bytes
*/
@ -1858,7 +1767,6 @@ int ipq9574_edma_hw_init(struct ipq9574_edma_hw *ehw)
return 0;
}
#ifndef CONFIG_IPQ9574_RUMI
void get_phy_address(int offset)
{
int phy_type;
@ -1878,7 +1786,6 @@ void get_phy_address(int offset)
phy_info[i++]->phy_type = phy_type;
}
}
#endif
int ipq9574_edma_init(void *edma_board_cfg)
{
@ -1889,7 +1796,6 @@ int ipq9574_edma_init(void *edma_board_cfg)
int i;
int ret = -1;
ipq9574_edma_board_cfg_t ledma_cfg, *edma_cfg;
#ifndef CONFIG_IPQ9574_RUMI
int phy_id;
uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2;
static int sw_init_done = 0;
@ -1918,7 +1824,6 @@ int ipq9574_edma_init(void *edma_board_cfg)
printf("Error:switch_mac_mode0 not specified in dts");
return mode;
}
#endif
memset(c_info, 0, (sizeof(c_info) * IPQ9574_EDMA_DEV));
memset(enet_addr, 0, sizeof(enet_addr));
@ -1995,7 +1900,6 @@ int ipq9574_edma_init(void *edma_board_cfg)
ipq9574_edma_dev[i]->c_info = c_info[i];
ipq9574_edma_hw_addr = IPQ9574_EDMA_CFG_BASE;
#ifndef CONFIG_IPQ9574_RUMI
ret = ipq_sw_mdio_init(edma_cfg->phy_name);
if (ret)
goto init_failed;
@ -2068,7 +1972,6 @@ int ipq9574_edma_init(void *edma_board_cfg)
break;
}
}
#endif
ret = ipq9574_edma_hw_init(hw[i]);

30
drivers/net/ipq9574/ipq9574_edma.h
View file

@ -21,23 +21,27 @@
#define IPQ9574_NSS_DP_START_PHY_PORT 1
#define IPQ9574_NSS_DP_MAX_PHY_PORTS 6
#define IPQ9574_EDMA_BUF_SIZE 2000
#define IPQ9574_EDMA_DEVICE_NODE_NAME "edma"
#define IPQ9574_EDMA_RX_BUFF_SIZE (IPQ9574_EDMA_BUF_SIZE \
+ IPQ9574_EDMA_RX_SEC_DESC_SIZE)
/* Number of descriptors in each ring is defined with below macro */
#define EDMA_RING_SIZE 128
/* Number of byte in a descriptor is defined with below macros for each of
* the rings respectively */
#define IPQ9574_EDMA_TXDESC_DESC_SIZE (sizeof(struct ipq9574_edma_txdesc_desc))
#define IPQ9574_EDMA_TXCMPL_DESC_SIZE (sizeof(struct ipq9574_edma_txcmpl_desc))
#define IPQ9574_EDMA_RXDESC_DESC_SIZE (sizeof(struct ipq9574_edma_rxdesc_desc))
#define IPQ9574_EDMA_RXFILL_DESC_SIZE (sizeof(struct ipq9574_edma_rxfill_desc))
#define IPQ9574_EDMA_RX_SEC_DESC_SIZE (sizeof(struct ipq9574_edma_rx_sec_desc))
#define IPQ9574_EDMA_TX_SEC_DESC_SIZE (sizeof(struct ipq9574_edma_tx_sec_desc))
#define EDMA_RING_SIZE 128
#define IPQ9574_EDMA_TXDESC_RING_SIZE 32
#define IPQ9574_EDMA_TXCMPL_RING_SIZE 16
#define IPQ9574_EDMA_RXDESC_RING_SIZE 32
#define IPQ9574_EDMA_RXFILL_RING_SIZE 16
#define IPQ9574_EDMA_START_GMACS IPQ9574_NSS_DP_START_PHY_PORT
#define IPQ9574_EDMA_MAX_GMACS IPQ9574_NSS_DP_MAX_PHY_PORTS
#define IPQ9574_EDMA_TX_BUFF_SIZE (1540 + IPQ9574_EDMA_TX_SEC_DESC_SIZE)
#define IPQ9574_EDMA_TX_BUFF_SIZE 1572
#define IPQ9574_EDMA_RX_BUFF_SIZE 2048
/* Max number of rings of each type is defined with below macro */
#define IPQ9574_EDMA_MAX_TXCMPL_RINGS 32 /* Max TxCmpl rings */
#define IPQ9574_EDMA_MAX_RXDESC_RINGS 24 /* Max RxDesc rings */
#define IPQ9574_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */
@ -54,17 +58,19 @@
#define IPQ9574_EDMA_TX_QUEUE 1
#define IPQ9574_EDMA_RX_QUEUE 1
/* Only 1 ring of each type will be used in U-Boot which is defined with
* below macros */
#define IPQ9574_EDMA_TX_DESC_RING_START 23
#define IPQ9574_EDMA_TX_DESC_RING_NOS 1
#define IPQ9574_EDMA_TX_DESC_RING_SIZE \
(IPQ9574_EDMA_TX_DESC_RING_START + IPQ9574_EDMA_TX_DESC_RING_NOS)
#define IPQ9574_EDMA_SEC_TX_DESC_RING_START 23
#define IPQ9574_EDMA_SEC_TX_DESC_RING_START 31
#define IPQ9574_EDMA_SEC_TX_DESC_RING_NOS 1
#define IPQ9574_EDMA_SEC_TX_DESC_RING_SIZE \
(IPQ9574_EDMA_SEC_TX_DESC_RING_START + IPQ9574_EDMA_SEC_TX_DESC_RING_NOS)
#define IPQ9574_EDMA_TX_CMPL_RING_START 23
#define IPQ9574_EDMA_TX_CMPL_RING_START 31
#define IPQ9574_EDMA_TX_CMPL_RING_NOS 1
#define IPQ9574_EDMA_TX_CMPL_RING_SIZE \
(IPQ9574_EDMA_TX_CMPL_RING_START + IPQ9574_EDMA_TX_CMPL_RING_NOS)

140
drivers/net/ipq9574/ipq9574_ppe.c
View file

@ -19,9 +19,7 @@
#include <common.h>
#include <asm/global_data.h>
#include "ipq9574_ppe.h"
#ifndef CONFIG_IPQ9574_RUMI
#include "ipq9574_uniphy.h"
#endif
#include <fdtdec.h>
#include "ipq_phy.h"
@ -34,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define pr_info(fmt, args...) printf(fmt, ##args);
extern void uniphy_clk_init(void);
extern void uniphy_port5_clock_source_set(void);
/*
@ -190,7 +189,6 @@ void ppe_port_bridge_txmac_set(int port_id, int status)
}
#ifndef CONFIG_IPQ9574_RUMI
/*
* ipq9574_port_mac_clock_reset()
*/
@ -284,6 +282,7 @@ void ipq9574_port_mac_clock_reset(int port)
}
writel(reg_val, NSS_CC_PPE_RESET_ADDR);
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
mdelay(150);
}
void ipq9574_speed_clock_set(int port_id, int clk[4])
@ -468,14 +467,15 @@ void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex,
ppe_port_rxmac_status_set(port);
ppe_mac_packet_filter_set(port);
}
#endif
void ipq9574_pqsgmii_speed_set(int port, int speed, int status)
{
ppe_port_bridge_txmac_set(port + 1, status);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed);
uniphy_clk_init();
mdelay(150);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5);
}
/*
@ -626,6 +626,16 @@ static void ipq9574_ppe_tdm_configuration(void)
ipq9574_ppe_reg_write(0xc730, 0x35);
ipq9574_ppe_reg_write(0xc740, 0x20);
ipq9574_ppe_reg_write(0xc750, 0x36);
ipq9574_ppe_reg_write(0xc760, 0x2E);
ipq9574_ppe_reg_write(0xc770, 0x03);
ipq9574_ppe_reg_write(0xc780, 0x1A);
ipq9574_ppe_reg_write(0xc790, 0x1C);
ipq9574_ppe_reg_write(0xc7a0, 0x12);
ipq9574_ppe_reg_write(0xc7b0, 0x1);
ipq9574_ppe_reg_write(0xc7c0, 0xE);
ipq9574_ppe_reg_write(0xc7d0, 0x5);
ipq9574_ppe_reg_write(0xc7e0, 0x32);
ipq9574_ppe_reg_write(0xc7f0, 0x31);
ipq9574_ppe_reg_write(0xb000, 0x80000076);
}
@ -634,65 +644,65 @@ static void ipq9574_ppe_tdm_configuration(void)
*/
static void ipq9574_ppe_sched_configuration(void)
{
ipq9574_ppe_reg_write(0x0047a000, 0xCF65);
ipq9574_ppe_reg_write(0x0047a010, 0x9F76);
ipq9574_ppe_reg_write(0x0047a020, 0x3F17);
ipq9574_ppe_reg_write(0x0047a030, 0x3F56);
ipq9574_ppe_reg_write(0x0047a040, 0xBD01);
ipq9574_ppe_reg_write(0x0047a050, 0xDD65);
ipq9574_ppe_reg_write(0x0047a060, 0xDE20);
ipq9574_ppe_reg_write(0x0047a070, 0xDE65);
ipq9574_ppe_reg_write(0x0047a080, 0x9F06);
ipq9574_ppe_reg_write(0x0047a090, 0xBB52);
ipq9574_ppe_reg_write(0x0047a0a0, 0xFA60);
ipq9574_ppe_reg_write(0x0047a0b0, 0xBE56);
ipq9574_ppe_reg_write(0x0047a0c0, 0x9F05);
ipq9574_ppe_reg_write(0x0047a0d0, 0xDE60);
ipq9574_ppe_reg_write(0x0047a0e0, 0x7E57);
ipq9574_ppe_reg_write(0x0047a0f0, 0x5F65);
ipq9574_ppe_reg_write(0x0047a100, 0x9F76);
ipq9574_ppe_reg_write(0x0047a110, 0xBE30);
ipq9574_ppe_reg_write(0x0047a120, 0xBE56);
ipq9574_ppe_reg_write(0x0047a130, 0xB703);
ipq9574_ppe_reg_write(0x0047a140, 0xD765);
ipq9574_ppe_reg_write(0x0047a150, 0xDE40);
ipq9574_ppe_reg_write(0x0047a160, 0xDE65);
ipq9574_ppe_reg_write(0x0047a170, 0x9F06);
ipq9574_ppe_reg_write(0x0047a180, 0xAF54);
ipq9574_ppe_reg_write(0x0047a190, 0xEE60);
ipq9574_ppe_reg_write(0x0047a1a0, 0xBE16);
ipq9574_ppe_reg_write(0x0047a1b0, 0x9F25);
ipq9574_ppe_reg_write(0x0047a1c0, 0xDE60);
ipq9574_ppe_reg_write(0x0047a1d0, 0x7E57);
ipq9574_ppe_reg_write(0x0047a1e0, 0x5F05);
ipq9574_ppe_reg_write(0x0047a1f0, 0x9F36);
ipq9574_ppe_reg_write(0x0047a200, 0xBE50);
ipq9574_ppe_reg_write(0x0047a210, 0xBE76);
ipq9574_ppe_reg_write(0x0047a220, 0xBD01);
ipq9574_ppe_reg_write(0x0047a230, 0xDD65);
ipq9574_ppe_reg_write(0x0047a240, 0x9F06);
ipq9574_ppe_reg_write(0x0047a250, 0x9F75);
ipq9574_ppe_reg_write(0x0047a260, 0xDE60);
ipq9574_ppe_reg_write(0x0047a270, 0xFA52);
ipq9574_ppe_reg_write(0x0047a280, 0xDB05);
ipq9574_ppe_reg_write(0x0047a290, 0x9F76);
ipq9574_ppe_reg_write(0x0047a2a0, 0x9F05);
ipq9574_ppe_reg_write(0x0047a2b0, 0x9F16);
ipq9574_ppe_reg_write(0x0047a2c0, 0xBE50);
ipq9574_ppe_reg_write(0x0047a2d0, 0xDE65);
ipq9574_ppe_reg_write(0x0047a2e0, 0x9F06);
ipq9574_ppe_reg_write(0x0047a2f0, 0x9F25);
ipq9574_ppe_reg_write(0x0047a300, 0x9F06);
ipq9574_ppe_reg_write(0x0047a310, 0xBE50);
ipq9574_ppe_reg_write(0x0047a320, 0xBE65);
ipq9574_ppe_reg_write(0x0047a330, 0x9F36);
ipq9574_ppe_reg_write(0x0047a340, 0x9F05);
ipq9574_ppe_reg_write(0x0047a350, 0x9F46);
ipq9574_ppe_reg_write(0x0047a360, 0xBE50);
ipq9574_ppe_reg_write(0x0047a370, 0x7E67);
ipq9574_ppe_reg_write(0x0047a380, 0x7753);
ipq9574_ppe_reg_write(0x0047a390, 0xF660);
ipq9574_ppe_reg_write(0x0047a3a0, 0xEE54);
ipq9574_ppe_reg_write(0x0047a000, 0x15CF65);
ipq9574_ppe_reg_write(0x0047a010, 0x159F76);
ipq9574_ppe_reg_write(0x0047a020, 0x153F17);
ipq9574_ppe_reg_write(0x0047a030, 0x153F56);
ipq9574_ppe_reg_write(0x0047a040, 0x15BD01);
ipq9574_ppe_reg_write(0x0047a050, 0x15DD65);
ipq9574_ppe_reg_write(0x0047a060, 0x15DE20);
ipq9574_ppe_reg_write(0x0047a070, 0x15DE65);
ipq9574_ppe_reg_write(0x0047a080, 0x159F06);
ipq9574_ppe_reg_write(0x0047a090, 0x15BB52);
ipq9574_ppe_reg_write(0x0047a0a0, 0x15FA60);
ipq9574_ppe_reg_write(0x0047a0b0, 0x15BE56);
ipq9574_ppe_reg_write(0x0047a0c0, 0x159F05);
ipq9574_ppe_reg_write(0x0047a0d0, 0x15DE60);
ipq9574_ppe_reg_write(0x0047a0e0, 0x157E57);
ipq9574_ppe_reg_write(0x0047a0f0, 0x155F65);
ipq9574_ppe_reg_write(0x0047a100, 0x159F76);
ipq9574_ppe_reg_write(0x0047a110, 0x15BE30);
ipq9574_ppe_reg_write(0x0047a120, 0x15BE56);
ipq9574_ppe_reg_write(0x0047a130, 0x15B703);
ipq9574_ppe_reg_write(0x0047a140, 0x15D765);
ipq9574_ppe_reg_write(0x0047a150, 0x15DE40);
ipq9574_ppe_reg_write(0x0047a160, 0x15DE65);
ipq9574_ppe_reg_write(0x0047a170, 0x159F06);
ipq9574_ppe_reg_write(0x0047a180, 0x15AF54);
ipq9574_ppe_reg_write(0x0047a190, 0x15EE60);
ipq9574_ppe_reg_write(0x0047a1a0, 0x15BE16);
ipq9574_ppe_reg_write(0x0047a1b0, 0x159F25);
ipq9574_ppe_reg_write(0x0047a1c0, 0x15DE60);
ipq9574_ppe_reg_write(0x0047a1d0, 0x157E57);
ipq9574_ppe_reg_write(0x0047a1e0, 0x155F05);
ipq9574_ppe_reg_write(0x0047a1f0, 0x159F36);
ipq9574_ppe_reg_write(0x0047a200, 0x15BE50);
ipq9574_ppe_reg_write(0x0047a210, 0x15BE76);
ipq9574_ppe_reg_write(0x0047a220, 0x15BD01);
ipq9574_ppe_reg_write(0x0047a230, 0x15DD65);
ipq9574_ppe_reg_write(0x0047a240, 0x159F06);
ipq9574_ppe_reg_write(0x0047a250, 0x159F75);
ipq9574_ppe_reg_write(0x0047a260, 0x15DE60);
ipq9574_ppe_reg_write(0x0047a270, 0x15FA52);
ipq9574_ppe_reg_write(0x0047a280, 0x15DB05);
ipq9574_ppe_reg_write(0x0047a290, 0x159F76);
ipq9574_ppe_reg_write(0x0047a2a0, 0x159F05);
ipq9574_ppe_reg_write(0x0047a2b0, 0x159F16);
ipq9574_ppe_reg_write(0x0047a2c0, 0x15BE50);
ipq9574_ppe_reg_write(0x0047a2d0, 0x15DE65);
ipq9574_ppe_reg_write(0x0047a2e0, 0x159F06);
ipq9574_ppe_reg_write(0x0047a2f0, 0x159F25);
ipq9574_ppe_reg_write(0x0047a300, 0x159F06);
ipq9574_ppe_reg_write(0x0047a310, 0x15BE50);
ipq9574_ppe_reg_write(0x0047a320, 0x15BE65);
ipq9574_ppe_reg_write(0x0047a330, 0x159F36);
ipq9574_ppe_reg_write(0x0047a340, 0x159F05);
ipq9574_ppe_reg_write(0x0047a350, 0x159F46);
ipq9574_ppe_reg_write(0x0047a360, 0x15BE50);
ipq9574_ppe_reg_write(0x0047a370, 0x157E67);
ipq9574_ppe_reg_write(0x0047a380, 0x157753);
ipq9574_ppe_reg_write(0x0047a390, 0x15F660);
ipq9574_ppe_reg_write(0x0047a3a0, 0x15EE54);
ipq9574_ppe_reg_write(0x00400000, 0x3b);
}
@ -834,11 +844,9 @@ void ipq9574_ppe_interface_mode_init(void)
return;
}
#ifndef CONFIG_IPQ9574_RUMI
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2);
#endif
/*
*

41
drivers/net/ipq9574/ipq9574_uniphy.c
View file

@ -179,23 +179,25 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
else
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
mdelay(100);
writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
if (uniphy_index == 0) {
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
} else if (uniphy_index == 1) {
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
} else {
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
}
mdelay(100);
ppe_uniphy_calibration(uniphy_index);
ipq9574_qca8075_phy_serdes_reset(0x10);
}
@ -208,21 +210,24 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
else
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
mdelay(100);
writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
if (uniphy_index == 0) {
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
} else if (uniphy_index == 1) {
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
} else {
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
}
mdelay(100);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
@ -242,6 +247,7 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
else
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
mdelay(100);
if (uniphy_index == 1) {
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
@ -280,17 +286,18 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
if (uniphy_index == 0) {
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
} else if (uniphy_index == 1) {
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
} else {
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
}
mdelay(100);
if (uniphy_index == 1) {
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
@ -339,17 +346,18 @@ static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
if (uniphy_index == 0) {
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
} else if (uniphy_index == 1) {
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
} else {
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
}
mdelay(100);
ppe_uniphy_calibration(uniphy_index);
@ -381,23 +389,25 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
else
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
mdelay(100);
writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
if (uniphy_index == 0) {
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
} else if (uniphy_index == 1) {
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
} else {
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
udelay(500);
mdelay(100);
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
}
mdelay(100);
ppe_uniphy_calibration(uniphy_index);
@ -407,6 +417,7 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
else
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false);
mdelay(100);
ppe_uniphy_10g_r_linkup(uniphy_index);
reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS);

1
include/configs/ipq9574.h
View file

@ -297,6 +297,7 @@ extern loff_t board_env_size;
#define CONFIG_IPQ9574_BRIDGED_MODE 1
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_SYS_RX_ETH_BUFFER 128
#define CONFIG_TFTP_BLOCKSIZE 1280
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_MII