Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

arch/arm/dts/zynq-zc706.dts

@@ -18,6 +18,7 @@
 		i2c0 = &i2c0;
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -291,6 +292,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdhci0_default>;

arch/arm/dts/zynq-zed.dts

@@ -17,6 +17,7 @@
 		ethernet0 = &gem0;
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -50,6 +51,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 

arch/arm/dts/zynq-zybo.dts

@@ -16,6 +16,8 @@
 	aliases {
 		ethernet0 = &gem0;
 		serial0 = &uart1;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
@@ -28,6 +30,10 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
 };
 
 &clkc {
@@ -45,6 +51,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
@@ -52,3 +59,14 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

arch/arm/mach-zynq/Kconfig

@@ -33,7 +33,6 @@ config TARGET_ZYNQ_ZC770
 
 config TARGET_ZYNQ_ZYBO
 	bool "Zynq Zybo Board"
-	select ZYNQ_CUSTOM_INIT
 
 endchoice
 

arch/microblaze/Kconfig

@@ -11,6 +11,8 @@ choice
 config TARGET_MICROBLAZE_GENERIC
 	bool "Support microblaze-generic"
 	select SUPPORT_SPL
+	select OF_CONTROL
+	select DM
 
 endchoice
 

board/xilinx/microblaze-generic/microblaze-generic.c

@@ -69,6 +69,7 @@ int dram_init(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_XILINX_GPIO
 	if (reset_pin != -1)
 		gpio_direction_output(reset_pin, 1);
@@ -77,7 +78,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_XILINX_TB_WATCHDOG
 	hw_watchdog_disable();
 #endif
-
+#endif
 	puts ("Reseting board\n");
 	__asm__ __volatile__ ("	mts rmsr, r0;" \
 				"bra r0");
@@ -122,40 +123,5 @@ int board_eth_init(bd_t *bis)
 			txpp, rxpp);
 #endif
 
-#ifdef CONFIG_XILINX_LL_TEMAC
-# ifdef XILINX_LLTEMAC_BASEADDR
-#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
-#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
-#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_DCR,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-#   else
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_PLB,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-#   endif
-#  endif
-# endif
-# ifdef XILINX_LLTEMAC_BASEADDR1
-#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
-#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
-#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_SDMA_DCR,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-#   else
-	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
-			XILINX_LL_TEMAC_M_SDMA_PLB,
-			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-#   endif
-#  endif
-# endif
-#endif
-
 	return ret;
 }

board/xilinx/microblaze-generic/xparameters.h

@@ -56,12 +56,6 @@
 /* Ethernet controller is Ethernet_MAC */
 #define XILINX_EMACLITE_BASEADDR       0x40C00000
 
-/* LL_TEMAC Ethernet controller */
-#define XILINX_LLTEMAC_BASEADDR			0x44000000
-#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
-#define XILINX_LLTEMAC_BASEADDR1		0x44200000
-#define XILINX_LLTEMAC_FIFO_BASEADDR1		0x42100000
-
 /* Watchdog IP is wxi_timebase_wdt_0 */
 #define XILINX_WATCHDOG_BASEADDR	0x50000000
 #define XILINX_WATCHDOG_IRQ		1

board/xilinx/zynq/Makefile

@@ -12,6 +12,7 @@ hw-platform-$(CONFIG_TARGET_ZYNQ_ZED)		:= zed_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED)	:= MicroZed_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702)		:= ZC702_hw_platform
 hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706)		:= ZC706_hw_platform
+hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO)		:= zybo_hw_platform
 # If you want to use customized ps7_init_gpl.c/h,
 # enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
 # This line must be placed at the bottom of the list because

board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int  u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
+#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
+#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
+#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  650000000
+#define DDR_FREQ  525000000
+#define DCI_FREQ  10096154
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  108333336
+#define WDT_FREQ  108333336
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  175000000
+#define FPGA2_FREQ  12264151
+#define FPGA3_FREQ  100000000
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif

configs/microblaze-generic_defconfig

@@ -1,9 +1,9 @@
 CONFIG_MICROBLAZE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y

configs/zynq_microzed_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_picozed_defconfig

@@ -8,5 +8,4 @@ CONFIG_SPL=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc702_defconfig

@@ -14,7 +14,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_ZYNQ=y

configs/zynq_zc706_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_zc770_xm010_defconfig

@@ -17,7 +17,6 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_zc770_xm011_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc770_xm012_defconfig

@@ -10,5 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zc770_xm013_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y

configs/zynq_zed_defconfig

@@ -15,6 +15,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y

configs/zynq_zybo_defconfig

@@ -11,9 +11,11 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_ZYNQ_QSPI=y

drivers/net/Kconfig

@@ -103,8 +103,9 @@ config PCH_GBE
 
 config ZYNQ_GEM
 	depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
+	select PHYLIB
 	bool "Xilinx Ethernet GEM"
 	help
-	  This MAC is presetn in Xilinx Zynq and ZynqMP SoCs.
+	  This MAC is present in Xilinx Zynq and ZynqMP SoCs.
 
 endif # NETDEVICES

drivers/net/zynq_gem.c

@@ -27,10 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if !defined(CONFIG_PHYLIB)
-# error XILINX_GEM_ETHERNET requires PHYLIB
-#endif
-
 /* Bit/mask specification */
 #define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK	0x20000000 /* read operation */
@@ -532,46 +528,57 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	int frame_len;
+	u32 addr;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
-	struct emac_bd *first_bd;
 
 	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
-		return 0;
+		return -1;
 
 	if (!(current_bd->status &
 			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
 		printf("GEM: SOF or EOF not set for last buffer received!\n");
-		return 0;
+		return -1;
 	}
 
 	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
-	if (frame_len) {
+	if (!frame_len) {
-		u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+		printf("%s: Zero size packet?\n", __func__);
-		addr &= ~(ARCH_DMA_MINALIGN - 1);
+		return -1;
-
-		net_process_received_packet((u8 *)(ulong)addr, frame_len);
-
-		if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
-			priv->rx_first_buf = priv->rxbd_current;
-		else {
-			current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
-			current_bd->status = 0xF0000000; /* FIXME */
-		}
-
-		if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
-			first_bd = &priv->rx_bd[priv->rx_first_buf];
-			first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
-			first_bd->status = 0xF0000000;
-		}
-
-		if ((++priv->rxbd_current) >= RX_BUF)
-			priv->rxbd_current = 0;
 	}
 
+	addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+	addr &= ~(ARCH_DMA_MINALIGN - 1);
+	*packetp = (uchar *)(uintptr_t)addr;
+
 	return frame_len;
 }
 
+static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	struct zynq_gem_priv *priv = dev_get_priv(dev);
+	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
+	struct emac_bd *first_bd;
+
+	if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
+		priv->rx_first_buf = priv->rxbd_current;
+	} else {
+		current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+		current_bd->status = 0xF0000000; /* FIXME */
+	}
+
+	if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
+		first_bd = &priv->rx_bd[priv->rx_first_buf];
+		first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+		first_bd->status = 0xF0000000;
+	}
+
+	if ((++priv->rxbd_current) >= RX_BUF)
+		priv->rxbd_current = 0;
+
+	return 0;
+}
+
 static void zynq_gem_halt(struct udevice *dev)
 {
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
@@ -651,6 +658,7 @@ static const struct eth_ops zynq_gem_ops = {
 	.start			= zynq_gem_init,
 	.send			= zynq_gem_send,
 	.recv			= zynq_gem_recv,
+	.free_pkt		= zynq_gem_free_pkt,
 	.stop			= zynq_gem_halt,
 	.write_hwaddr		= zynq_gem_setup_mac,
 };
@@ -666,11 +674,12 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 	priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
 	/* Hardcode for now */
 	priv->emio = 0;
+	priv->phyaddr = -1;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 				       "phy-handle");
 	if (offset > 0)
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
+		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 	if (phy_mode)

drivers/spi/zynq_qspi.c

@@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK	BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */
@@ -68,6 +69,9 @@ struct zynq_qspi_regs {
 	u32 txd1r;	/* 0x80 */
 	u32 txd2r;	/* 0x84 */
 	u32 txd3r;	/* 0x88 */
+	u32 reserved1[5];
+	u32 lqspicfg;	/* 0xA0 */
+	u32 lqspists;	/* 0xA4 */
 };
 
 /* zynq qspi platform data */
@@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
 		ZYNQ_QSPI_CR_MSTREN_MASK;
 	writel(confr, &regs->cr);
 
+	/* Disable the LQSPI feature */
+	confr = readl(&regs->lqspicfg);
+	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+	writel(confr, &regs->lqspicfg);
+
 	/* Enable SPI */
 	writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 }

include/configs/microblaze-generic.h

@@ -68,10 +68,6 @@
 # define CONFIG_XILINX_EMACLITE	1
 # define CONFIG_SYS_ENET
 #endif
-#if defined(XILINX_LLTEMAC_BASEADDR)
-# define CONFIG_XILINX_LL_TEMAC	1
-# define CONFIG_SYS_ENET
-#endif
 #if defined(XILINX_AXIEMAC_BASEADDR)
 # define CONFIG_XILINX_AXIEMAC	1
 # define CONFIG_SYS_ENET
@@ -101,8 +97,10 @@
 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
 # define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
 # define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
-# define CONFIG_HW_WATCHDOG
+# ifndef CONFIG_SPL_BUILD
-# define CONFIG_XILINX_TB_WATCHDOG
+#  define CONFIG_HW_WATCHDOG
+#  define CONFIG_XILINX_TB_WATCHDOG
+# endif
 #endif
 
 #if !defined(CONFIG_OF_CONTROL) || \
@@ -113,15 +111,10 @@
 #endif
 
 #define CONFIG_SYS_MALLOC_LEN	0xC0000
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_SYS_MALLOC_F_LEN	1024
-#else
-# define CONFIG_SYS_MALLOC_SIMPLE
-# define CONFIG_SYS_MALLOC_F_LEN	0x150
-#endif
 
 /* Stack location before relocation */
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
+					 CONFIG_SYS_MALLOC_F_LEN)
 
 /*
  * CFI flash memory layout - Example
@@ -360,7 +353,7 @@
 #define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 
-#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
+#if defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII		1
 # define CONFIG_CMD_MII		1
 # define CONFIG_PHY_GIGE	1

include/configs/xilinx_zynqmp.h

@@ -188,7 +188,6 @@
 # define CONFIG_NET_MULTI
 # define CONFIG_MII
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_PHYLIB
 # define CONFIG_PHY_MARVELL
 # define CONFIG_PHY_TI
 #endif

include/configs/zynq_zybo.h

@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_BOOT_FREEBSD
 

net/eth.c

@@ -541,6 +541,34 @@ static int eth_post_probe(struct udevice *dev)
 	struct eth_pdata *pdata = dev->platdata;
 	unsigned char env_enetaddr[6];
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	struct eth_ops *ops = eth_get_ops(dev);
+	static int reloc_done;
+
+	if (!reloc_done) {
+		if (ops->start)
+			ops->start += gd->reloc_off;
+		if (ops->send)
+			ops->send += gd->reloc_off;
+		if (ops->recv)
+			ops->recv += gd->reloc_off;
+		if (ops->free_pkt)
+			ops->free_pkt += gd->reloc_off;
+		if (ops->stop)
+			ops->stop += gd->reloc_off;
+#ifdef CONFIG_MCAST_TFTP
+		if (ops->mcast)
+			ops->mcast += gd->reloc_off;
+#endif
+		if (ops->write_hwaddr)
+			ops->write_hwaddr += gd->reloc_off;
+		if (ops->read_rom_hwaddr)
+			ops->read_rom_hwaddr += gd->reloc_off;
+
+		reloc_done++;
+	}
+#endif
+
 	priv->state = ETH_STATE_INIT;
 
 	/* Check if the device has a MAC address in ROM */

tools/zynqimage.c

@@ -212,8 +212,7 @@ static int zynqimage_check_params(struct image_tool_params *params)
 		return -1;
 	}
 
-	return !((params->lflag || params->dflag) ||
+	return !(params->lflag || params->dflag);
-			(params->dflag && params->eflag));
 }
 
 static int zynqimage_check_image_types(uint8_t type)