From 1c7d57b963bd4392d3ddda24f102b0db782fd5e6 Mon Sep 17 00:00:00 2001 From: Antony Arun T Date: Tue, 20 Nov 2018 14:51:38 +0530 Subject: [PATCH] ipq6018: Skip uboot relocation and setup CP15 barrier Change-Id: I29ced10a3ab0f36a06bdbb642f6b73ab287e8d6d Signed-off-by: Antony Arun T --- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/lib/cache-cp15.c | 2 +- common/board_f.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 45b86f74d2..bb7b4fd910 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -48,7 +48,7 @@ save_boot_params_ret: msr cpsr,r0 /* Setup CP15 barrier */ -#if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ806x) +#if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ806x) || defined (CONFIG_ARCH_IPQ6018) mrc p15, 0, r0, c1, c0, 0 @Read SCTLR to r0 orr r0, r0, #0x20 @set the cp15 barrier enable bit mcr p15, 0, r0, c1, c0, 0 @write back to SCTLR diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 2a1153033d..0f7f8e26ec 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -62,7 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x) +#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ6018) #define UBOOT_CACHE_SETUP 0x100e #define GEN_CACHE_SETUP 0x101e diff --git a/common/board_f.c b/common/board_f.c index a5042f5dd0..e48b92bcab 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1062,7 +1062,7 @@ void board_init_f(ulong boot_flags) gd->flags = boot_flags; gd->have_console = 0; -#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) +#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ6018) gd->flags |= GD_FLG_SKIP_RELOC; #endif