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u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default

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This patch disables MPC8548CDS 2T_TIMING for DDR by default.

Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
This commit is contained in:
ebony.zhu@freescale.com 2006-12-18 16:25:15 +08:00 • committed by Andrew Fleming-AFLEMING
parent 41fb7e0f1e
commit 39b18c4f3e
1 changed files with 1 additions and 1 deletions
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2
include/configs/MPC8548CDS.h
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@ -41,7 +41,7 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */