ipq807x: mmc: Added emmc clock configurations

Change-Id: I61454a90ec9723e22b4b3ca3d76f1c4b8a03a331
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
This commit is contained in:
Vasudevan Murugesan 2016-06-10 16:07:14 +05:30 committed by Gerrit - the friendly Code Review server
parent e452f79755
commit 3983a7aa1d
2 changed files with 43 additions and 1 deletions

View file

@ -57,7 +57,38 @@ void reset_cpu(unsigned long a)
void emmc_clock_config(int mode)
{
/* TODO: To be filled */
/* Enable root clock generator */
writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR);
/* Add 10us delay for CLK_OFF to get cleared */
udelay(10);
if (mode == MMC_IDENTIFY_MODE) {
/* XO - 400Khz*/
writel(0x2017, GCC_SDCC1_APPS_CFG_RCGR);
/* Delay for clock operation complete */
udelay(10);
writel(0x1, GCC_SDCC1_APPS_M);
writel(0xFC, GCC_SDCC1_APPS_N);
writel(0xFD, GCC_SDCC1_APPS_D);
/* Delay for clock operation complete */
udelay(10);
}
if (mode == MMC_DATA_TRANSFER_MODE) {
/* PLL0 - 50Mhz */
writel(0x40F, GCC_SDCC1_APPS_CFG_RCGR);
/* Delay for clock operation complete */
udelay(10);
writel(0x1, GCC_SDCC1_APPS_M);
writel(0xFC, GCC_SDCC1_APPS_N);
writel(0xFD, GCC_SDCC1_APPS_D);
/* Delay for clock operation complete */
udelay(10);
}
/* Update APPS_CMD_RCGR to reflect source selection */
writel(readl(GCC_SDCC1_APPS_CMD_RCGR)|0x1, GCC_SDCC1_APPS_CMD_RCGR);
/* Add 10us delay for clock update to complete */
udelay(10);
}
int board_mmc_init(bd_t *bis)

View file

@ -17,4 +17,15 @@
#include <configs/ipq807x.h>
#include <asm/u-boot.h>
/*
* GCC-SDCC Registers
*/
#define GCC_SDCC1_MISC 0x1842020
#define GCC_SDCC1_APPS_CBCR 0x1842018
#define GCC_SDCC1_APPS_CFG_RCGR 0x1842008
#define GCC_SDCC1_APPS_CMD_RCGR 0x1842004
#define GCC_SDCC1_APPS_M 0x184200C
#define GCC_SDCC1_APPS_N 0x1842010
#define GCC_SDCC1_APPS_D 0x1842014
#endif /* _IPQ807X_H_ */