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ipq807x: mmc: Added emmc clock configurations
Change-Id: I61454a90ec9723e22b4b3ca3d76f1c4b8a03a331 Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
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parent
e452f79755
commit
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2 changed files with 43 additions and 1 deletions
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@ -57,7 +57,38 @@ void reset_cpu(unsigned long a)
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void emmc_clock_config(int mode)
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{
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/* TODO: To be filled */
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/* Enable root clock generator */
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writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR);
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/* Add 10us delay for CLK_OFF to get cleared */
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udelay(10);
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if (mode == MMC_IDENTIFY_MODE) {
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/* XO - 400Khz*/
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writel(0x2017, GCC_SDCC1_APPS_CFG_RCGR);
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/* Delay for clock operation complete */
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udelay(10);
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writel(0x1, GCC_SDCC1_APPS_M);
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writel(0xFC, GCC_SDCC1_APPS_N);
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writel(0xFD, GCC_SDCC1_APPS_D);
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/* Delay for clock operation complete */
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udelay(10);
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}
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if (mode == MMC_DATA_TRANSFER_MODE) {
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/* PLL0 - 50Mhz */
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writel(0x40F, GCC_SDCC1_APPS_CFG_RCGR);
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/* Delay for clock operation complete */
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udelay(10);
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writel(0x1, GCC_SDCC1_APPS_M);
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writel(0xFC, GCC_SDCC1_APPS_N);
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writel(0xFD, GCC_SDCC1_APPS_D);
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/* Delay for clock operation complete */
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udelay(10);
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}
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/* Update APPS_CMD_RCGR to reflect source selection */
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writel(readl(GCC_SDCC1_APPS_CMD_RCGR)|0x1, GCC_SDCC1_APPS_CMD_RCGR);
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/* Add 10us delay for clock update to complete */
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udelay(10);
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}
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int board_mmc_init(bd_t *bis)
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@ -17,4 +17,15 @@
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#include <configs/ipq807x.h>
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#include <asm/u-boot.h>
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/*
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* GCC-SDCC Registers
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*/
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#define GCC_SDCC1_MISC 0x1842020
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#define GCC_SDCC1_APPS_CBCR 0x1842018
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#define GCC_SDCC1_APPS_CFG_RCGR 0x1842008
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#define GCC_SDCC1_APPS_CMD_RCGR 0x1842004
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#define GCC_SDCC1_APPS_M 0x184200C
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#define GCC_SDCC1_APPS_N 0x1842010
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#define GCC_SDCC1_APPS_D 0x1842014
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#endif /* _IPQ807X_H_ */
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