diff --git a/drivers/net/ipq5332/ipq5332_edma.c b/drivers/net/ipq5332/ipq5332_edma.c
index 8747304920..0d4183e775 100644
--- a/drivers/net/ipq5332/ipq5332_edma.c
+++ b/drivers/net/ipq5332/ipq5332_edma.c
@@ -91,7 +91,8 @@ static int tftp_acl_our_port;
 
 #ifdef CONFIG_QCA8084_BYPASS_MODE
 extern void qca8084_bypass_interface_mode_set(u32 interface_mode);
-extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
+extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode,
+		u32 link, fal_port_speed_t speed);
 static int qca8084_bypass_enb = 0;
 #endif /* CONFIG_QCA8084_BYPASS_MODE */
 
@@ -1166,11 +1167,11 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
 		if (phy_info->phy_type == QCA8084_PHY_TYPE) {
 			if (curr_speed[i] == FAL_SPEED_2500) {
 				qca8084_phy_sgmii_mode_set(PORT4,
-						PORT_SGMII_PLUS);
+						PORT_SGMII_PLUS, status, curr_speed[i]);
 			}
 			else {
 				qca8084_phy_sgmii_mode_set(PORT4,
-						PHY_SGMII_BASET);
+						PHY_SGMII_BASET, status, curr_speed[i]);
 			}
 		}
 #endif /* CONFIG_QCA8084_BYPASS_MODE */
diff --git a/drivers/net/ipq_common/ipq_qca8084.c b/drivers/net/ipq_common/ipq_qca8084.c
index 325736dafa..493701bca4 100644
--- a/drivers/net/ipq_common/ipq_qca8084.c
+++ b/drivers/net/ipq_common/ipq_qca8084.c
@@ -68,7 +68,8 @@ bool qca8084_port_rxfc_forcemode[QCA8084_MAX_PORTS] = {};
 #endif /* CONFIG_QCA8084_SWT_MODE */
 
 #ifdef CONFIG_QCA8084_BYPASS_MODE
-extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
+extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode,
+		u32 link, fal_port_speed_t speed);
 #endif /* CONFIG_QCA8084_BYPASS_MODE */
 
 static int qca8084_reg_field_get(u32 reg_addr, u32 bit_offset,
@@ -1449,10 +1450,45 @@ void ipq_qca8084_switch_hw_reset(int gpio)
 #endif /* CONFIG_QCA8084_SWT_MODE */
 
 #ifdef CONFIG_QCA8084_BYPASS_MODE
+void qca8084_phy_sgmii_speed_fixup (u32 phy_addr, u32 link,
+		fal_port_speed_t new_speed)
+{
+	/*disable ethphy3 and uniphy0 clock*/
+	pr_debug("disable ethphy3 and uniphy0 clock\n");
+	qca8084_port_clk_en_set(PORT4, QCA8084_CLK_TYPE_EPHY, false);
+	qca8084_port_clk_en_set(PORT5, QCA8084_CLK_TYPE_UNIPHY, false);
+
+	/*set gmii clock for ethphy3 and uniphy0*/
+	pr_debug("set speed clock for eth3 and uniphy0\n");
+	qca8084_port_speed_clock_set(PORT4, new_speed);
+
+	/*uniphy and ethphy gmii clock enable/disable*/
+	pr_debug("uniphy and ethphy GMII clock enable/disable\n");
+	if(!link)
+	{
+		pr_debug("enable ethphy3 and uniphy0 clock\n");
+		qca8084_port_clk_en_set(PORT4, QCA8084_CLK_TYPE_EPHY, true);
+		qca8084_port_clk_en_set(PORT5, QCA8084_CLK_TYPE_UNIPHY, true);
+	}
+	/*uniphy and ethphy gmii reset and release*/
+	pr_debug("uniphy and ethphy GMII interface reset and release\n");
+	qca8084_port_clk_reset(PORT4, QCA8084_CLK_TYPE_EPHY);
+	qca8084_port_clk_reset(PORT5, QCA8084_CLK_TYPE_UNIPHY);
+
+	/*uniphy and ethphy ipg_tune reset, function reset*/
+	pr_debug("uniphy and ethphy ipg_tune reset, function reset\n");
+	qca8084_uniphy_sgmii_function_reset(QCA8084_UNIPHY_SGMII_0);
+
+	/*do ethphy function reset*/
+	pr_debug("do ethphy function reset\n");
+	qca8084_phy_function_reset(phy_addr);
+	return;
+}
+
 void qca8084_bypass_interface_mode_set(u32 interface_mode)
 {
 	ipq_qca8084_work_mode_set(QCA8084_PHY_SGMII_UQXGMII_MODE);
-	qca8084_phy_sgmii_mode_set(PORT4, interface_mode);
+	qca8084_phy_sgmii_mode_set(PORT4, interface_mode, false, FAL_SPEED_1000);
 
 	pr_debug("ethphy3 software reset\n");
 	qca8084_phy_reset(PORT4);
diff --git a/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c b/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c
index f53c1de417..05af73faa0 100644
--- a/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c
+++ b/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c
@@ -50,6 +50,11 @@ extern void qca8084_uniphy_raw_clock_set(qca8084_clk_parent_t uniphy_clk,
 		uint64_t rate);
 #endif
 
+#ifdef CONFIG_QCA8084_BYPASS_MODE
+extern void qca8084_phy_sgmii_speed_fixup (u32 phy_addr, u32 link,
+		fal_port_speed_t new_speed);
+#endif
+
 void qca8084_serdes_addr_get(uint32_t serdes_id, uint32_t *address)
 {
 	uint32_t data = 0;
@@ -665,7 +670,8 @@ uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index,
 #endif /* CONFIG_QCA8084_SWT_MODE */
 
 #ifdef CONFIG_QCA8084_BYPASS_MODE
-void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode)
+void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode,
+		u32 link, fal_port_speed_t speed)
 {
 	uint32_t phy_addr_tmp = 0;
 	mac_config_t config = {0};
@@ -692,6 +698,8 @@ void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode)
 
 	qca8084_interface_sgmii_mode_set(QCA8084_UNIPHY_SGMII_0,
 			PORT4, &config);
+
+	qca8084_phy_sgmii_speed_fixup(phy_addr, link, speed);
 	return;
 }
 #endif /* CONFIG_QCA8084_BYPASS_MODE */