mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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qca: ipq40xx: Add ess driver
Change-Id: If5f6ab192c5fca57296f9213404abcd6bb16bfb7 Signed-off-by: Balamurugan Selvarajan <bselvara@codeaurora.org>
This commit is contained in:
Balamurugan Selvarajan
Akila N
parent
84ba768fc3
commit
3522c2faad
2 changed files with 511 additions and 0 deletions
330
drivers/net/ipq40xx/ipq40xx_ess_sw.c
Normal file
330
drivers/net/ipq40xx/ipq40xx_ess_sw.c
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@ -0,0 +1,330 @@
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/*
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <net.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include "ipq40xx_ess_sw.h"
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#include "ipq40xx.h"
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extern board_ipq40xx_params_t *gboard_param;
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static inline void ipq40xx_ess_sw_rd(u32 addr, u32 * data)
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{
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*data = readl((void __iomem *)(IPQ40XX_NSS_BASE + addr));
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}
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static inline void ipq40xx_ess_sw_wr(u32 addr, u32 data)
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{
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writel(data, ((void __iomem *)(IPQ40XX_NSS_BASE + addr)));
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}
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void ipq40xx_ess_disable_lookup(void)
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{
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ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x14001c);
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ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x14001a);
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ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140016);
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ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x14001e);
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ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3e3e3e);
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}
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void ipq40xx_ess_enable_lookup(void)
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{
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ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x14003e);
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ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x14001d);
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ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x14001b);
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ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140017);
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ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x14000f);
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ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140001);
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ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3f3f3f);
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}
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int ipq40xx_ess_sw_init(ipq40xx_edma_board_cfg_t *cfg)
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{
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u32 data;
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ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3e3e3e);
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/*
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* configure Speed, Duplex.
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*/
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ipq40xx_ess_sw_wr(S17_P0STATUS_REG, S17_PORT_SPEED(2) |
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S17_PORT_FULL_DUP |
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S17_TX_FLOW_EN |
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S17_RX_FLOW_EN);
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switch(gboard_param->machid) {
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case MACH_TYPE_IPQ40XX_AP_DK01_1_S1:
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case MACH_TYPE_IPQ40XX_AP_DK01_1_C1:
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case MACH_TYPE_IPQ40XX_AP_DK01_1_C2:
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case MACH_TYPE_IPQ40XX_AP_DK04_1_C1:
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case MACH_TYPE_IPQ40XX_AP_DK04_1_C4:
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case MACH_TYPE_IPQ40XX_AP_DK04_1_C2:
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case MACH_TYPE_IPQ40XX_AP_DK04_1_C3:
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case MACH_TYPE_IPQ40XX_AP_DK06_1_C1:
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case MACH_TYPE_IPQ40XX_AP_DK07_1_C1:
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ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x140000);
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ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140000);
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/*
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* HOL setting for Port0
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*/
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ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL0, 0x1e444444);
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ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL1, 0x1c6);
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/*
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* HOL setting for Port1
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*/
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ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL0, 0x1e004444);
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ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL1, 0x1c6);
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/*
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* HOL setting for Port2
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*/
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ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL0, 0x1e004444);
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ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL1, 0x1c6);
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/*
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* HOL setting for Port3
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*/
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ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL0, 0x1e004444);
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ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL1, 0x1c6);
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/*
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* HOL setting for Port4
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*/
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ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL0, 0x1e004444);
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ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL1, 0x1c6);
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/*
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* HOL setting for Port5
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*/
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ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL0, 0x1e444444);
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ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL1, 0x1c6);
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break;
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case MACH_TYPE_IPQ40XX_DB_DK02_1_C1:
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case MACH_TYPE_IPQ40XX_DB_DK01_1_C1:
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ipq40xx_ess_sw_wr(S17_P4STATUS_REG, S17_PORT_SPEED(2) |
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S17_PORT_FULL_DUP |
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S17_TX_FLOW_EN |
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S17_RX_FLOW_EN |
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S17_PORT_TX_MAC_EN |
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S17_PORT_RX_MAC_EN);
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ipq40xx_ess_sw_wr(S17_P5STATUS_REG, S17_PORT_SPEED(2) |
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S17_PORT_FULL_DUP |
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S17_TX_FLOW_EN |
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S17_RX_FLOW_EN |
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S17_PORT_TX_MAC_EN |
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S17_PORT_RX_MAC_EN);
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ipq40xx_ess_sw_wr(ESS_MIB_REG, 0x100000);
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ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x34006f);;
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break;
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default:
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printf("ess cfg not supported for %x machid\n",
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gboard_param->machid);
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return -1;
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}
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mdelay(1);
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/*
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* Enable Rx and Tx mac.
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*/
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ipq40xx_ess_sw_rd(S17_P0STATUS_REG, &data);
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ipq40xx_ess_sw_wr(S17_P0STATUS_REG, data |
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S17_PORT_TX_MAC_EN |
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S17_PORT_RX_MAC_EN);
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ipq40xx_ess_sw_rd(ESS_MIB_OFFSET, &data);
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ipq40xx_ess_sw_wr(ESS_MIB_OFFSET, data |
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ESS_MIB_EN);
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ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x7f7f7f);
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printf ("%s done\n", __func__);
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return 0;
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}
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#ifdef CONFIG_ESS_MIB_EN
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static void ess_dump_stats(struct ess_rx_stats *rx,
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struct ess_tx_stats *tx, u32 port)
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{
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/*
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* Tx stats
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*/
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printf ("########tx port: %d stats ########\n", port);
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printf("port: %d tx_broadcast: %d\n", port, tx->tx_broad);
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printf("port: %d tx_pause: %d\n", port, tx->tx_pause);
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printf("port: %d tx_multi: %d\n", port, tx->tx_multi);
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printf("port: %d tx_underrun: %d\n", port, tx->tx_underrun);
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printf("port: %d tx_64 byte: %d\n", port, tx->tx_64b);
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printf("port: %d tx_128 byte: %d\n", port, tx->tx_128b);
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printf("port: %d tx_256 byte: %d\n", port, tx->tx_256b);
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printf("port: %d tx_512 byte: %d\n", port, tx->tx_512b);
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printf("port: %d tx_1024 byte: %d\n", port, tx->tx_1024b);
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printf("port: %d tx_1518 byte: %d\n", port, tx->tx_1518b);
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printf("port: %d tx_max byte: %d\n", port, tx->tx_maxb);
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printf("port: %d tx_oversize: %d\n", port, tx->tx_oversiz);
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printf("port: %d tx_byte_lo: %d\n", port, tx->tx_bytel);
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printf("port: %d tx_byte_hi: %d\n", port, tx->tx_byteh);
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printf("port: %d tx_collision: %d\n", port, tx->tx_collision);
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printf("port: %d tx_abort_col: %d\n", port, tx->tx_abortcol);
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printf("port: %d tx_multi_col: %d\n", port, tx->tx_multicol);
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printf("port: %d tx_singla_col: %d\n", port, tx->tx_singalcol);
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printf("port: %d tx_exec_defer: %d\n", port, tx->tx_execdefer);
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printf("port: %d tx_defer: %d\n", port, tx->tx_defer);
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printf("port: %d tx_late_col: %d\n", port, tx->tx_latecol);
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printf("port: %d tx_unicast: %d\n", port, tx->tx_unicast);
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/*
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* rx stats
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*/
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printf ("########rx port: %d stats ########\n\n", port);
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printf("port: %d rx_broadcast: %d\n", port, rx->rx_broad);
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printf("port: %d rx_pause: %d\n", port, rx->rx_pause);
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printf("port: %d rx_multi: %d\n", port, rx->rx_multi);
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printf("port: %d rx_fcserr: %d\n", port, rx->rx_fcserr);
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printf("port: %d rx_allignerr: %d\n", port, rx->rx_allignerr);
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printf("port: %d rx_runt: %d\n", port, rx->rx_runt);
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printf("port: %d rx_frag: %d\n", port, rx->rx_frag);
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printf("port: %d rx_64 byte: %d\n", port, rx->rx_64b);
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printf("port: %d rx_128 byte: %d\n", port, rx->rx_128b);
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printf("port: %d rx_256 byte: %d\n", port, rx->rx_256b);
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printf("port: %d rx_512 byte: %d\n", port, rx->rx_512b);
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printf("port: %d rx_1024 byte: %d\n", port, rx->rx_1024b);
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printf("port: %d rx_1518 byte: %d\n", port, rx->rx_1518b);
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printf("port: %d rx_max byte: %d\n", port, rx->rx_maxb);
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printf("port: %d rx_too long: %d\n", port, rx->rx_tool);
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printf("port: %d rx_good byte lo: %d\n", port, rx->rx_goodbl);
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printf("port: %d rx_good byte hi: %d\n", port, rx->rx_goodbh);
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printf("port: %d rx overflow: %d\n", port, rx->rx_overflow);
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printf("port: %d rx_bad lo: %d\n", port, rx->rx_badbl);
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printf("port: %d rx_bad hi: %d\n", port, rx->rx_badbu);
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printf("port: %d rx unicast: %d\n", port, rx->rx_unicast);
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}
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static int ipq40xx_ess_stats(cmd_tbl_t *cmdtp, int flag,
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int argc, char *const argv[])
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{
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struct ess_rx_stats rx_mib;
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struct ess_tx_stats tx_mib;
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u32 portno;
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unsigned long timebase;
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if (argc != 2)
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return CMD_RET_USAGE;
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portno = simple_strtoul(argv[1], NULL, 16);
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if (portno > 6)
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return CMD_RET_USAGE;
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/*
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* Tx stats
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*/
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_BROAD_REG), &tx_mib.tx_broad);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_PAUSE_REG), &tx_mib.tx_pause);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_MULTI_REG), &tx_mib.tx_multi);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_MULTI_REG), &tx_mib.tx_underrun);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_64B_REG), &tx_mib.tx_64b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_128B_REG), &tx_mib.tx_128b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_256B_REG), &tx_mib.tx_256b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_512B_REG), &tx_mib.tx_512b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_1024B_REG), &tx_mib.tx_1024b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_1518B_REG), &tx_mib.tx_1518b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_MAXB_REG), &tx_mib.tx_maxb);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_OVSIZE_REG), &tx_mib.tx_oversiz);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_TXBYTEL_REG), &tx_mib.tx_bytel);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_TXBYTEU_REG), &tx_mib.tx_byteh);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_COLL_REG), &tx_mib.tx_collision);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_ABTCOLL_REG), &tx_mib.tx_abortcol);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_MLTCOL_REG), &tx_mib.tx_multicol);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_SINGCOL_REG), &tx_mib.tx_singalcol);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_EXDF_REG), &tx_mib.tx_execdefer);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_DEF_REG), &tx_mib.tx_defer);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_LATECOL_REG), &tx_mib.tx_latecol);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_TX_UNICAST), &tx_mib.tx_unicast);
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/*
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* Rx stats
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*/
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_BROAD_REG), &rx_mib.rx_broad);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_PAUSE_REG), &rx_mib.rx_pause);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_MULTI_REG), &rx_mib.rx_multi);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_FCSERR_REG), &rx_mib.rx_fcserr);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_ALIGNERR_REG), &rx_mib.rx_allignerr);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_RUNT_REG), &rx_mib.rx_runt);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_FRAGMENT_REG), &rx_mib.rx_frag);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_RUNT_REG), &rx_mib.rx_64b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_128B_REG), &rx_mib.rx_128b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_phy_RX_256B_REG), &rx_mib.rx_256b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_512B_REG), &rx_mib.rx_512b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_1024B_REG), &rx_mib.rx_1024b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_1518B_REG), &rx_mib.rx_1518b);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_MAXB_REG), &rx_mib.rx_maxb);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_TOLO_REG), &rx_mib.rx_tool);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_GOODBL_REG), &rx_mib.rx_goodbl);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_GOODBU_REG), &rx_mib.rx_goodbh);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
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ESS_PHY_RX_OVERFLW_REG), rx_mib.rx_overflow);
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ipq40xx_ess_sw_rd((ess_mib(portno) |
|
||||
ESS_PHY_RX_BADBL_REG), &rx_mib.rx_badbl);
|
||||
ipq40xx_ess_sw_rd((ess_mib(portno) |
|
||||
ESS_PHY_RX_BADBL_REG), &rx_mib.rx_badbu);
|
||||
ipq40xx_ess_sw_rd((ess_mib(portno) |
|
||||
ESS_PHY_RX_UNICAST), &rx_mib.rx_unicast);
|
||||
/*
|
||||
* Dump stats
|
||||
*/
|
||||
ess_dump_stats(&rx_mib, &tx_mib, portno);
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(essstats, 2, 0, ipq40xx_ess_stats,
|
||||
"get ess mib stats for the given ess port",
|
||||
"essstats <0 - 5>");
|
||||
#endif
|
||||
|
||||
181
drivers/net/ipq40xx/ipq40xx_ess_sw.h
Normal file
181
drivers/net/ipq40xx/ipq40xx_ess_sw.h
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
|
||||
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _AR8327_PHY_H
|
||||
#define _AR8327_PHY_H
|
||||
#define IPQ40XX_NSS_BASE 0xC000000
|
||||
|
||||
#define S17_P0STATUS_REG 0x007c
|
||||
#define S17_P1STATUS_REG 0x0080
|
||||
#define S17_P2STATUS_REG 0x0084
|
||||
#define S17_P3STATUS_REG 0x0088
|
||||
#define S17_P4STATUS_REG 0x008c
|
||||
#define S17_P5STATUS_REG 0x0090
|
||||
#define S17_P6STATUS_REG 0x0094
|
||||
|
||||
#define S17_PORT_SPEED(x) (x << 0)
|
||||
#define S17_TX_FLOW_EN (1 << 4)
|
||||
#define S17_RX_FLOW_EN (1 << 5)
|
||||
#define S17_PORT_TX_MAC_EN (1 << 2)
|
||||
#define S17_PORT_RX_MAC_EN (1 << 3)
|
||||
#define S17_PORT_FULL_DUP (1 << 6)
|
||||
|
||||
#define S17_GLOFW_CTRL1_REG 0x0624
|
||||
#define S17_GLOLEARN_LIMIT_REG 0x0628
|
||||
#define S17_TOS_PRIMAP_REG0 0x0630
|
||||
#define S17_TOS_PRIMAP_REG1 0x0634
|
||||
#define S17_TOS_PRIMAP_REG2 0x0638
|
||||
#define S17_TOS_PRIMAP_REG3 0x063c
|
||||
#define S17_TOS_PRIMAP_REG4 0x0640
|
||||
#define S17_TOS_PRIMAP_REG5 0x0644
|
||||
#define S17_TOS_PRIMAP_REG6 0x0648
|
||||
#define S17_TOS_PRIMAP_REG7 0x064c
|
||||
#define S17_VLAN_PRIMAP_REG0 0x0650
|
||||
#define S17_LOOP_CHECK_REG 0x0654
|
||||
#define S17_P0LOOKUP_CTRL_REG 0x0660
|
||||
#define S17_P0PRI_CTRL_REG 0x0664
|
||||
#define S17_P0LEARN_LMT_REG 0x0668
|
||||
#define S17_P1LOOKUP_CTRL_REG 0x066c
|
||||
#define S17_P1PRI_CTRL_REG 0x0670
|
||||
#define S17_P1LEARN_LMT_REG 0x0674
|
||||
#define S17_P2LOOKUP_CTRL_REG 0x0678
|
||||
#define S17_P2PRI_CTRL_REG 0x067c
|
||||
#define S17_P2LEARN_LMT_REG 0x0680
|
||||
#define S17_P3LOOKUP_CTRL_REG 0x0684
|
||||
#define S17_P3PRI_CTRL_REG 0x0688
|
||||
#define S17_P3LEARN_LMT_REG 0x068c
|
||||
#define S17_P4LOOKUP_CTRL_REG 0x0690
|
||||
#define S17_P4PRI_CTRL_REG 0x0694
|
||||
#define S17_P4LEARN_LMT_REG 0x0698
|
||||
#define S17_P5LOOKUP_CTRL_REG 0x069c
|
||||
|
||||
/* Queue Management Registers */
|
||||
#define S17_PORT0_HOL_CTRL0 0x0970
|
||||
#define S17_PORT0_HOL_CTRL1 0x0974
|
||||
#define S17_PORT1_HOL_CTRL0 0x0978
|
||||
#define S17_PORT1_HOL_CTRL1 0x097c
|
||||
#define S17_PORT2_HOL_CTRL0 0x0980
|
||||
#define S17_PORT2_HOL_CTRL1 0x0984
|
||||
#define S17_PORT3_HOL_CTRL0 0x0988
|
||||
#define S17_PORT3_HOL_CTRL1 0x098c
|
||||
#define S17_PORT4_HOL_CTRL0 0x0990
|
||||
#define S17_PORT4_HOL_CTRL1 0x0994
|
||||
#define S17_PORT5_HOL_CTRL0 0x0998
|
||||
#define S17_PORT5_HOL_CTRL1 0x099c
|
||||
|
||||
#define ess_mib(x) ((0x1000 | (x * 0x100)))
|
||||
#define ESS_MIB_OFFSET 0x30
|
||||
#define ESS_MIB_REG 0x34
|
||||
#define ESS_MIB_EN (1 << 0)
|
||||
#ifdef CONFIG_ESS_MIB_EN
|
||||
/*
|
||||
* Tx Mib counter offset
|
||||
*/
|
||||
#define ESS_PHY_TX_BROAD_REG 0x54
|
||||
#define ESS_PHY_TX_PAUSE_REG 0x58
|
||||
#define ESS_PHY_TX_MULTI_REG 0x5c
|
||||
#define ESS_PHY_TX_UNDERRN_REG 0x60
|
||||
#define ESS_PHY_TX_64B_REG 0x64
|
||||
#define ESS_PHY_TX_128B_REG 0x68
|
||||
#define ESS_PHY_TX_256B_REG 0x6c
|
||||
#define ESS_PHY_TX_512B_REG 0x70
|
||||
#define ESS_PHY_TX_1024B_REG 0x74
|
||||
#define ESS_PHY_TX_1518B_REG 0x78
|
||||
#define ESS_PHY_TX_MAXB_REG 0x7c
|
||||
#define ESS_PHY_TX_OVSIZE_REG 0x80
|
||||
#define ESS_PHY_TX_TXBYTEL_REG 0x88
|
||||
#define ESS_PHY_TX_TXBYTEU_REG 0x84
|
||||
#define ESS_PHY_TX_COLL_REG 0x8c
|
||||
#define ESS_PHY_TX_ABTCOLL_REG 0x90
|
||||
#define ESS_PHY_TX_MLTCOL_REG 0x94
|
||||
#define ESS_PHY_TX_SINGCOL_REG 0x98
|
||||
#define ESS_PHY_TX_EXDF_REG 0x9c
|
||||
#define ESS_PHY_TX_DEF_REG 0xA0
|
||||
#define ESS_PHY_TX_LATECOL_REG 0xA4
|
||||
#define ESS_PHY_TX_UNICAST 0xAc
|
||||
/*
|
||||
* Rx Mib counter offset
|
||||
*/
|
||||
#define ESS_PHY_RX_BROAD_REG 0x00
|
||||
#define ESS_PHY_RX_PAUSE_REG 0x04
|
||||
#define ESS_PHY_RX_MULTI_REG 0x08
|
||||
#define ESS_PHY_RX_FCSERR_REG 0x0c
|
||||
#define ESS_PHY_RX_ALIGNERR_REG 0x10
|
||||
#define ESS_PHY_RX_RUNT_REG 0x14
|
||||
#define ESS_PHY_RX_FRAGMENT_REG 0x18
|
||||
#define ESS_PHY_RX_64B_REG 0x1c
|
||||
#define ESS_PHY_RX_128B_REG 0x20
|
||||
#define ESS_phy_RX_256B_REG 0x24
|
||||
#define ESS_PHY_RX_512B_REG 0x28
|
||||
#define ESS_PHY_RX_1024B_REG 0x2c
|
||||
#define ESS_PHY_RX_1518B_REG 0x30
|
||||
#define ESS_PHY_RX_MAXB_REG 0x34
|
||||
#define ESS_PHY_RX_TOLO_REG 0x38
|
||||
#define ESS_PHY_RX_GOODBL_REG 0x40
|
||||
#define ESS_PHY_RX_GOODBU_REG 0x3c
|
||||
#define ESS_PHY_RX_BADBL_REG 0x48
|
||||
#define ESS_PHY_RX_BADBU_REG 0x44
|
||||
#define ESS_PHY_RX_OVERFLW_REG 0x4c
|
||||
#define ESS_PHY_RX_FILTERD_REG 0x50
|
||||
#define ESS_PHY_RX_UNICAST 0xA8
|
||||
|
||||
struct ess_rx_stats {
|
||||
u32 rx_broad;
|
||||
u32 rx_pause;
|
||||
u32 rx_multi;
|
||||
u32 rx_fcserr;
|
||||
u32 rx_allignerr;
|
||||
u32 rx_runt;
|
||||
u32 rx_frag;
|
||||
u32 rx_64b;
|
||||
u32 rx_128b;
|
||||
u32 rx_256b;
|
||||
u32 rx_512b;
|
||||
u32 rx_1024b;
|
||||
u32 rx_1518b;
|
||||
u32 rx_maxb;
|
||||
u32 rx_tool;
|
||||
u32 rx_goodbl;
|
||||
u32 rx_goodbh;
|
||||
u32 rx_overflow;
|
||||
u32 rx_badbl;
|
||||
u32 rx_badbu;
|
||||
u32 rx_unicast;
|
||||
};
|
||||
|
||||
struct ess_tx_stats{
|
||||
u32 tx_broad;
|
||||
u32 tx_pause;
|
||||
u32 tx_multi;
|
||||
u32 tx_underrun;
|
||||
u32 tx_64b;
|
||||
u32 tx_128b;
|
||||
u32 tx_256b;
|
||||
u32 tx_512b;
|
||||
u32 tx_1024b;
|
||||
u32 tx_1518b;
|
||||
u32 tx_maxb;
|
||||
u32 tx_oversiz;
|
||||
u32 tx_bytel;
|
||||
u32 tx_byteh;
|
||||
u32 tx_collision;
|
||||
u32 tx_abortcol;
|
||||
u32 tx_multicol;
|
||||
u32 tx_singalcol;
|
||||
u32 tx_execdefer;
|
||||
u32 tx_defer;
|
||||
u32 tx_latecol;
|
||||
u32 tx_unicast;
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue