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Merge "ipq9574: update usb phy sequence"

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Linux Build Service Account 2021-07-29 09:08:54 -07:00 • committed by Gerrit - the friendly Code Review server
commit 33dcec400e
1 changed files with 18 additions and 13 deletions
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31
board/qca/arm/ipq9574/ipq9574.c
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@ -256,39 +256,41 @@ static void usb_init_hsphy(void __iomem *phybase)
static void usb_init_ssphy(void __iomem *phybase)
{
out_8(phybase + USB3_PHY_POWER_DOWN_CONTROL,0x1);
out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x14);
out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x1a);
out_8(phybase + QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08);
out_8(phybase + QSERDES_COM_CLK_SELECT,0x30);
out_8(phybase + QSERDES_COM_BG_TRIM,0x0f);
out_8(phybase + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b);
out_8(phybase + QSERDES_COM_SVS_MODE_CLK_SEL,0x01);
out_8(phybase + QSERDES_COM_HSCLK_SEL,0x00);
out_8(phybase + QSERDES_COM_CMN_CONFIG,0x06);
out_8(phybase + QSERDES_COM_PLL_IVCO,0x0f);
out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x02);
out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x82);
out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0x55);
out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0x55);
out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x03);
out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x0b);
out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x06);
out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x68);
out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0xAB);
out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0xAA);
out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x02);
out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x09);
out_8(phybase + QSERDES_COM_PLL_RCTRL_MODE0,0x16);
out_8(phybase + QSERDES_COM_PLL_CCTRL_MODE0,0x28);
out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0x80);
out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0x15);
out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x34);
out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0xA0);
out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0xAA);
out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x29);
out_8(phybase + QSERDES_COM_LOCK_CMP3_MODE0,0x00);
out_8(phybase + QSERDES_COM_CORE_CLK_EN,0x00);
out_8(phybase + QSERDES_COM_LOCK_CMP_CFG,0x00);
out_8(phybase + QSERDES_COM_VCO_TUNE_MAP,0x00);
out_8(phybase + QSERDES_COM_BG_TIMER,0x0a);
out_8(phybase + QSERDES_COM_SSC_EN_CENTER,0x01);
out_8(phybase + QSERDES_COM_SSC_PER1,0x31);
out_8(phybase + QSERDES_COM_SSC_PER1,0x7D);
out_8(phybase + QSERDES_COM_SSC_PER2,0x01);
out_8(phybase + QSERDES_COM_SSC_ADJ_PER1,0x00);
out_8(phybase + QSERDES_COM_SSC_ADJ_PER2,0x00);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0xde);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x07);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0x0A);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x05);
out_8(phybase + QSERDES_RX_UCDR_SO_GAIN,0x06);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8);
out_8(phybase + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL,0x77);
@ -320,6 +322,9 @@ static void usb_init_ssphy(void __iomem *phybase)
out_8(phybase + PCS_RCVR_DTCT_DLY_U3_L,0x40);
out_8(phybase + PCS_RCVR_DTCT_DLY_U3_H,0x00);
out_8(phybase + PCS_RX_SIGDET_LVL,0x88);
out_8(phybase + USB3_PCS_TXDEEMPH_M6DB_V0,0x17);
out_8(phybase + USB3_PCS_TXDEEMPH_M3P5DB_V0,0x0f);
out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0);
out_8(phybase + USB3_PHY_START_CONTROL,0x03);
out_8(phybase + USB3_PHY_SW_RESET,0x00);
}