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arm: dts: Add MI01.13 (RDP480) dts support.

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RDP480 IPQ5332 + QCN9224 + QCN6432 + QCN9160 (2+4+2+Y)

Change-Id: Ibd36002d30c563932da501901c0e1504e1c33d8f
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This commit is contained in:
Saahil Tomar 2023-11-06 11:47:58 +05:30 • committed by Rajkumar Ayyasamy
parent 1be88b4e84
commit 33bf8df37a
4 changed files with 302 additions and 1 deletions
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1
arch/arm/dts/Makefile
View file

@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-emulation.dtb \
ipq5332-mi01.6.dtb \
ipq5332-mi01.9.dtb \
ipq5332-mi01.12.dtb \
ipq5332-mi01.13.dtb \
ipq5332-mi03.1.dtb \
ipq5332-mi04.1.dtb \
ipq5332-mi04.3.dtb \

298
arch/arm/dts/ipq5332-mi01.13.dts Normal file
View file

@ -0,0 +1,298 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "ipq5332-soc.dtsi"
/ {
machid = <0x8060402>;
config_name = "config@mi01.13", "config@rdp480", "config-rdp480";
aliases {
console = "/serial@78AF000";
nand = "/nand-controller@79B0000";
mmc = "/sdhci@7804000";
usb0 = "/xhci@8a00000";
i2c0 = "/i2c@78B6000";
pci0 = "/pci@20000000";
pci1 = "/pci@18000000";
pci2 = "/pci@10000000";
};
serial@78AF000 {
status = "ok";
serial_gpio {
blsp0_uart_rx {
gpio = <18>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
blsp0_uart_tx {
gpio = <19>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
};
};
spi {
spi_gpio {
blsp0_spi_clk {
gpio = <14>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_mosi {
gpio = <15>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_miso {
gpio = <16>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_cs {
gpio = <17>;
func = <1>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
i2c@78B6000 {
i2c_gpio {
gpio1 {
gpio = <29>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
gpio2 {
gpio = <30>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
};
};
nand: nand-controller@79B0000 {
nand_gpio {
qspi_dat3 {
gpio = <8>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat2 {
gpio = <9>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat1 {
gpio = <10>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat0 {
gpio = <11>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_cs_n {
gpio = <12>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
qspi_clk {
gpio = <13>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
};
};
mmc: sdhci@7804000 {
mmc_gpio {
emmc_dat3 {
gpio = <8>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat2 {
gpio = <9>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat1 {
gpio = <10>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat0 {
gpio = <11>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_cmd{
gpio = <12>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_clk{
gpio = <13>;
func = <1>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_8MA>;
};
};
};
pci0: pci@20000000 {
status = "ok";
perst_gpio = <38>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <38>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <47>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci2: pci@10000000 {
status = "ok";
perst_gpio = <44>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <44>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
qca8084_switch_enable = <1>;
sfp_gpio = <24>;
sfp_gpio_cnt = <1>;
mdio_gpio {
mdc1 {
gpio = <27>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
};
mdio {
gpio = <28>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
};
};
port_phyinfo {
port@0 {
phy_address = <1>;
uniphy_id = <0>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
port@1 {
phy_type = <SFP_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
};
};
qca8084_swt_info {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
port@0 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
port@1 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@4 {
phy_address = <0x4>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@5 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
};
};
};

1
arch/arm/include/asm/mach-types.h
View file

@ -1184,6 +1184,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_IPQ5332_AP_MI04_1_C2 0x8060007
#define MACH_TYPE_IPQ5332_AP_MI04_3 0x8060107
#define MACH_TYPE_IPQ5332_AP_MI01_12 0x8060202
#define MACH_TYPE_IPQ5332_AP_MI01_13 0x8060402
#define MACH_TYPE_IPQ5332_AP_MI01_14 0x8060302
#ifdef CONFIG_ARCH_EBSA110

3
board/qca/arm/ipq5332/ipq5332.c
View file

@ -851,8 +851,9 @@ unsigned int get_dts_machid(unsigned int machid)
case MACH_TYPE_IPQ5332_AP_MI01_2_C2:
return MACH_TYPE_IPQ5332_AP_MI01_2;
case MACH_TYPE_IPQ5332_AP_MI01_3_C2:
case MACH_TYPE_IPQ5332_AP_MI01_7:
return MACH_TYPE_IPQ5332_AP_MI01_3;
case MACH_TYPE_IPQ5332_AP_MI01_7:
return MACH_TYPE_IPQ5332_AP_MI01_13;
case MACH_TYPE_IPQ5332_AP_MI01_14:
return MACH_TYPE_IPQ5332_AP_MI01_12;
case MACH_TYPE_IPQ5332_AP_MI04_1_C2: