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ipq9574: Add support for AP-AL02-C7 and AP-AL02-C8

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AP.AL02-C7 is similar to AP.AL02-C4 with emmc boot
Features: WK 2G + WK5G + WK 6G

AP.AL02-C8 is similar to AP.AL02-C6 with emmc boot
Features: Internal 2G +WK 5G + WK 6G

Change-Id: I31d1f65b071dfddc4eee393d292add58d3ddeadc
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2022-02-22 15:41:50 +05:30
parent a8451b0a27
commit 3367faaa3b
4 changed files with 120 additions and 0 deletions
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1
arch/arm/dts/Makefile
View file

@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_IPQ9574) += ipq9574-al01-c1.dtb \
ipq9574-al02-c2.dtb \
ipq9574-al02-c3.dtb \
ipq9574-al02-c4.dtb \
ipq9574-al02-c7.dtb \
ipq9574-db-al01-c1.dtb \
ipq9574-db-al01-c2.dtb \
ipq9574-db-al01-c3.dtb \

112
arch/arm/dts/ipq9574-al02-c7.dts Normal file
View file

@ -0,0 +1,112 @@
/*
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "ipq9574-al02-c4.dts"
/ {
machid = <0x8050601>;
config_name = "config@al02-c7";
aliases {
mmc = "/sdhci@7804000";
};
mmc: sdhci@7804000 {
compatible = "qcom,sdhci-msm";
status = "okay";
mmc_gpio {
emmc_dat7 {
gpio = <0>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat6 {
gpio = <1>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat5 {
gpio = <2>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat4 {
gpio = <3>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat3 {
gpio = <6>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat2 {
gpio = <7>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat1 {
gpio = <8>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_dat0 {
gpio = <9>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_cmd{
gpio = <4>;
func = <1>;
pull = <GPIO_PULL_UP>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_clk{
gpio = <5>;
func = <1>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
emmc_rclk{
gpio = <10>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
};
};
nand: nand-controller@79B0000 {
status = "disabled";
};
};

2
arch/arm/include/asm/mach-types.h
View file

@ -1160,9 +1160,11 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_IPQ807x_AP_HK10_C2 0x801010E
#define MACH_TYPE_IPQ9574_EMULATION 0xF050000
#define MACH_TYPE_IPQ9574_AP_AL02_C1 0x8050001
#define MACH_TYPE_IPQ9574_AP_AL02_C2 0x8050101
#define MACH_TYPE_IPQ9574_AP_AL02_C4 0x8050301
#define MACH_TYPE_IPQ9574_AP_AL02_C5 0x8050401
#define MACH_TYPE_IPQ9574_AP_AL02_C6 0x8050501
#define MACH_TYPE_IPQ9574_AP_AL02_C8 0x8050701
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type

5
board/qca/arm/ipq9574/ipq9574.c
View file

@ -1498,6 +1498,8 @@ unsigned int get_dts_machid(unsigned int machid)
return MACH_TYPE_IPQ9574_AP_AL02_C4;
case MACH_TYPE_IPQ9574_AP_AL02_C6:
return MACH_TYPE_IPQ9574_AP_AL02_C1;
case MACH_TYPE_IPQ9574_AP_AL02_C8:
return MACH_TYPE_IPQ9574_AP_AL02_C2;
default:
return machid;
}
@ -1519,6 +1521,9 @@ void ipq_uboot_fdt_fixup(void)
case MACH_TYPE_IPQ9574_AP_AL02_C6:
config = "config@al02-c6";
break;
case MACH_TYPE_IPQ9574_AP_AL02_C8:
config = "config@al02-c8";
break;
}
if (config != NULL)