From 33024894ca4de6dcbd6a0e6785155be262c843d2 Mon Sep 17 00:00:00 2001
From: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Date: Mon, 7 Dec 2020 14:24:54 +0530
Subject: [PATCH] ipq5018: Fix usb hsphy clock

It will resolve usb probe failure in hs phy
without ss phy. It enables utmi clock instead
of pipe clock in hs phy only configuration.

Change-Id: Idaf140d2cbe068304f1ce87c443c8e2196e3433e
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
---
 board/qca/arm/ipq5018/ipq5018.c | 16 ++++++++++++++--
 board/qca/arm/ipq5018/ipq5018.h |  4 ++++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c
index e08a3950b0..4d661d19da 100644
--- a/board/qca/arm/ipq5018/ipq5018.c
+++ b/board/qca/arm/ipq5018/ipq5018.c
@@ -1409,8 +1409,20 @@ static void usb_clock_init(int id, int ssphy)
 	writel(CLK_ENABLE, GCC_USB0_LFPS_CBCR);
 }
 
-static void usb_init_hsphy(void __iomem *phybase)
+static void usb_init_hsphy(void __iomem *phybase, int ssphy)
 {
+	if (!ssphy) {
+		/*Enable utmi instead of pipe*/
+		writel((readl(USB30_GENERAL_CFG) | PIPE_UTMI_CLK_DIS), USB30_GENERAL_CFG);
+
+		udelay(100);
+
+		writel((readl(USB30_GENERAL_CFG) | PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW), USB30_GENERAL_CFG);
+
+		udelay(100);
+
+		writel((readl(USB30_GENERAL_CFG) & ~PIPE_UTMI_CLK_DIS), USB30_GENERAL_CFG);
+	}
 	/* Disable USB PHY Power down */
 	setbits_le32(phybase + 0xA4, 0x1);
 	/* Enable override ctrl */
@@ -1480,7 +1492,7 @@ static void usb_init_phy(int index, int ssphy)
 
 	if (ssphy)
 		usb_init_ssphy((u32 *)USB3PHY_APB_BASE);
-	usb_init_hsphy((u32 *)QUSB2PHY_BASE);
+	usb_init_hsphy((u32 *)QUSB2PHY_BASE, ssphy);
 }
 
 int ipq_board_usb_init(void)
diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h
index 1a73ceca83..5f7ba7227f 100644
--- a/board/qca/arm/ipq5018/ipq5018.h
+++ b/board/qca/arm/ipq5018/ipq5018.h
@@ -234,6 +234,10 @@
 #define GUCTL					0x700C12C
 #define FLADJ					0x700C630
 
+#define PIPE_UTMI_CLK_SEL			0x1
+#define PIPE3_PHYSTATUS_SW			(0x1 << 3)
+#define PIPE_UTMI_CLK_DIS			(0x1 << 8)
+
 #define QUSB2PHY_BASE				0x5b000
 
 #define GCC_USB0_LFPS_CFG_SRC_SEL		(0x1 << 8)