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ipq807x: QPIC NAND Makefile and board file changes

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Change-Id: I67aeca19bcb7bdc5c83cb1fc6666cdb55bb24c37
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan 2016-06-01 10:33:59 +05:30
parent f07326d936
commit 32d68e6e5b
6 changed files with 83 additions and 25 deletions
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11
arch/arm/include/asm/arch-qcom-common/qpic_nand.h
View file

@ -30,10 +30,15 @@
#ifndef __QPIC_NAND_H
#define __QPIC_NAND_H
#define IPQ40xx_EBI2ND_BASE (0x079b0000)
#define IPQ40xx_QPIC_BAM_CTRL (0x07984000)
#if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI)
#define QPIC_EBI2ND_BASE (0x079b0000)
#else
#error "QPIC NAND not supported"
#endif
#define NAND_REG(off) (IPQ40xx_EBI2ND_BASE + (off))
#define QPIC_BAM_CTRL_BASE (0x07984000)
#define NAND_REG(off) (QPIC_EBI2ND_BASE + (off))
#define NAND_FLASH_CMD NAND_REG(0x0000)
#define NAND_ADDR0 NAND_REG(0x0004)

23
board/qca/ipq807x/ipq807x.c
View file

@ -18,6 +18,7 @@
#include "ipq807x.h"
#include "../common/qca_common.h"
#include <asm/arch-qcom-common/qpic_nand.h>
DECLARE_GLOBAL_DATA_PTR;
@ -103,3 +104,25 @@ int board_mmc_init(bd_t *bis)
return ret;
}
void board_nand_init(void)
{
struct qpic_nand_init_config config;
config.pipes.read_pipe = DATA_PRODUCER_PIPE;
config.pipes.write_pipe = DATA_CONSUMER_PIPE;
config.pipes.cmd_pipe = CMD_PIPE;
config.pipes.read_pipe_grp = DATA_PRODUCER_PIPE_GRP;
config.pipes.write_pipe_grp = DATA_CONSUMER_PIPE_GRP;
config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
config.bam_base = QPIC_BAM_CTRL_BASE;
config.nand_base = QPIC_EBI2ND_BASE;
config.ee = QPIC_NAND_EE;
config.max_desc_len = QPIC_NAND_MAX_DESC_LEN;
qpic_nand_init(&config);
}

1
drivers/dma/Makefile
View file

@ -11,3 +11,4 @@ obj-$(CONFIG_FSL_DMA) += fsl_dma.o
obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
obj-$(CONFIG_QCOM_BAM) += bam.o

1
drivers/mtd/nand/Makefile
View file

@ -68,6 +68,7 @@ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_DOCG4) += docg4.o
obj-$(CONFIG_QPIC_NAND) += qpic_nand.o
else # minimal SPL drivers

46
drivers/mtd/nand/qpic_nand.c
View file

@ -1174,7 +1174,7 @@ qpic_nand_mark_badblock(struct mtd_info *mtd, loff_t offs)
page = offs >> chip->page_shift;
ops.mode = MTD_OOB_RAW;
ops.mode = MTD_OPS_RAW;
ops.len = mtd->writesize;
ops.retlen = 0;
ops.ooblen = mtd->oobsize;
@ -1421,7 +1421,7 @@ static void qpic_nand_read_oobcopy(struct mtd_info *mtd,
return;
read_ooblen = ops->ooblen - ops->oobretlen;
ooblen = MIN(read_ooblen, dev->oob_per_page);
ooblen = (read_ooblen < dev->oob_per_page ? read_ooblen : dev->oob_per_page);
if (read_ooblen < dev->oob_per_page)
memcpy(ops->oobbuf + ops->oobretlen, dev->pad_oob, ooblen);
@ -1442,7 +1442,7 @@ static void qpic_nand_read_datcopy(struct mtd_info *mtd, struct mtd_oob_ops *ops
return;
read_datlen = ops->len - ops->retlen;
datlen = MIN(read_datlen, mtd->writesize);
datlen = (read_datlen < mtd->writesize ? read_datlen : mtd->writesize);
if (read_datlen < mtd->writesize)
memcpy(ops->datbuf + ops->retlen, dev->pad_dat, datlen);
@ -1689,7 +1689,7 @@ static int qpic_nand_read_oob(struct mtd_info *mtd, loff_t to,
enum nand_cfg_value cfg_mode;
/* We don't support MTD_OOB_PLACE as of yet. */
if (ops->mode == MTD_OOB_PLACE)
if (ops->mode == MTD_OPS_PLACE_OOB)
return -ENOSYS;
/* Check for reads past end of device */
@ -1702,7 +1702,7 @@ static int qpic_nand_read_oob(struct mtd_info *mtd, loff_t to,
if (ops->ooboffs != 0)
return -EINVAL;
if(ops->mode == MTD_OOB_RAW) {
if(ops->mode == MTD_OPS_RAW) {
cfg_mode = NAND_CFG_RAW;
dev->oob_per_page = mtd->oobsize;
} else {
@ -1767,7 +1767,7 @@ static int qpic_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
unsigned ret = 0;
struct mtd_oob_ops ops;
ops.mode = MTD_OOB_AUTO;
ops.mode = MTD_OPS_AUTO_OOB;
ops.len = len;
ops.retlen = 0;
ops.ooblen = 0;
@ -1840,7 +1840,7 @@ static void qpic_nand_write_oobinc(struct mtd_info *mtd,
return;
write_ooblen = ops->ooblen - ops->oobretlen;
ooblen = MIN(write_ooblen, dev->oob_per_page);
ooblen = (write_ooblen < dev->oob_per_page ? write_ooblen : dev->oob_per_page);
ops->oobretlen += ooblen;
}
@ -1858,7 +1858,7 @@ static int qpic_nand_write_oob(struct mtd_info *mtd, loff_t to,
enum nand_cfg_value cfg_mode;
/* We don't support MTD_OOB_PLACE as of yet. */
if (ops->mode == MTD_OOB_PLACE)
if (ops->mode == MTD_OPS_PLACE_OOB)
return -ENOSYS;
/* Check for writes past end of device. */
@ -1877,7 +1877,7 @@ static int qpic_nand_write_oob(struct mtd_info *mtd, loff_t to,
if (ops->datbuf == NULL)
return -EINVAL;
if(ops->mode == MTD_OOB_RAW) {
if(ops->mode == MTD_OPS_RAW) {
cfg_mode = NAND_CFG_RAW;
dev->oob_per_page = mtd->oobsize;
}
@ -1945,7 +1945,7 @@ static int qpic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
return NANDC_RESULT_PARAM_INVALID;
}
ops.mode = MTD_OOB_AUTO;
ops.mode = MTD_OPS_AUTO_OOB;
ops.len = len;
ops.retlen = 0;
ops.ooblen = 0;
@ -2104,18 +2104,20 @@ qpic_nand_mtd_params(struct mtd_info *mtd)
mtd->type = MTD_NANDFLASH;
mtd->flags = MTD_CAP_NANDFLASH;
mtd->erase = qpic_nand_erase;
mtd->point = NULL;
mtd->unpoint = NULL;
mtd->read = qpic_nand_read;
mtd->write = qpic_nand_write;
mtd->read_oob = qpic_nand_read_oob;
mtd->write_oob = qpic_nand_write_oob;
mtd->lock = NULL;
mtd->unlock = NULL;
mtd->block_isbad = qpic_nand_block_isbad;
mtd->block_markbad = qpic_nand_mark_badblock;
mtd->sync = qpic_nand_sync;
mtd->_erase = qpic_nand_erase;
#ifndef __UBOOT__
mtd->_point = NULL;
mtd->_unpoint = NULL;
#endif
mtd->_read = qpic_nand_read;
mtd->_write = qpic_nand_write;
mtd->_read_oob = qpic_nand_read_oob;
mtd->_write_oob = qpic_nand_write_oob;
mtd->_lock = NULL;
mtd->_unlock = NULL;
mtd->_block_isbad = qpic_nand_block_isbad;
mtd->_block_markbad = qpic_nand_mark_badblock;
mtd->_sync = qpic_nand_sync;
mtd->ecclayout = NULL;

26
include/configs/ipq807x.h
View file

@ -106,6 +106,32 @@
#define CONFIG_SPI_FLASH_BAR 1
#define CONFIG_EFI_PARTITION
#define CONFIG_QCOM_BAM 1
/*
* NAND Flash Configs
*/
/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode
* CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.
* BAM is enabled by default.
*/
#define CONFIG_QPIC_NAND
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_YAFFS
#define CONFIG_CMD_MEMORY
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
* Expose SPI driver as a pseudo NAND driver to make use
* of U-Boot's MTD framework.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_NAND_NAND_INFO_IDX 0
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
/*
* U-Boot Env Configs