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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 00:41:17 +01:00
Merge "arm: dts: ipq9574: Add QCA8084 switch support in AL02-C10"
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32bb34e1b8
5 changed files with 164 additions and 13 deletions
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@ -18,4 +18,45 @@
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machid = <0x8050901>;
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config_name = "config@al02-c10";
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ess-switch {
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/* Overriding config to support QCA8084 Switch instead of
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* QCA8084 PHY
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*/
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qca8084_switch_enable = <1>;
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switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
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qca8084_swt_info {
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switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
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switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
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port@0 {
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phy_address = <0xff>;
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phy_type = <UNUSED_PHY_TYPE>;
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forced-speed = <2500>;
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forced-duplex = <1>;
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};
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port@1 {
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phy_address = <1>;
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phy_type = <QCA8084_PHY_TYPE>;
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};
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port@2 {
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phy_address = <2>;
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phy_type = <QCA8084_PHY_TYPE>;
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};
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port@3 {
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phy_address = <3>;
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phy_type = <QCA8084_PHY_TYPE>;
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};
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port@4 {
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phy_address = <0x4>;
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phy_type = <QCA8084_PHY_TYPE>;
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};
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port@5 {
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phy_address = <0xff>;
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phy_type = <UNUSED_PHY_TYPE>;
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forced-speed = <2500>;
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forced-duplex = <1>;
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};
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};
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};
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};
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@ -46,6 +46,7 @@ static struct ipq9574_eth_dev *ipq9574_edma_dev[IPQ9574_EDMA_DEV];
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uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
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phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0};
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phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0};
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int sgmii_mode[2] = {0};
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extern void ipq_phy_addr_fixup(void);
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@ -62,8 +63,12 @@ extern int ipq_board_fw_download(unsigned int phy_addr);
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extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr);
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extern void qca8084_phy_uqxgmii_speed_fixup(uint32_t phy_addr, uint32_t qca8084_port_id,
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uint32_t status, fal_port_speed_t new_speed);
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extern int ipq_qca8084_hw_init(phy_info_t * phy_info[], int node);
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extern void ipq_qca8084_link_update(u32 port_id);
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extern void ipq_qca8084_switch_hw_reset(int gpio);
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static int tftp_acl_our_port;
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static int qca8084_swt_enb = 0;
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/*
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* EDMA hardware instance
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@ -1022,6 +1027,13 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], curr_speed[i],
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dp[duplex]);
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if ((phy_info[i]->phy_type == QCA8084_PHY_TYPE) && qca8084_swt_enb) {
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if (old_speed[i] != curr_speed[i]) {
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old_speed[i] = curr_speed[i];
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ipq_qca8084_link_update(phy_addr);
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}
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}
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continue;
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}
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@ -1257,17 +1269,22 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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}
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}
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ipq9574_speed_clock_set(i, clk);
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if (!qca8084_swt_enb || (i != PORT0))
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ipq9574_speed_clock_set(i, clk);
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if (phy_info[i]->phy_type == QCA8084_PHY_TYPE)
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qca8084_phy_uqxgmii_speed_fixup(phy_info[i]->phy_address, i + 1,
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status, curr_speed[i]);
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if (!qca8084_swt_enb && (phy_info[i]->phy_type == QCA8084_PHY_TYPE))
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qca8084_phy_uqxgmii_speed_fixup(phy_info[i]->phy_address,
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i + 1, status, curr_speed[i]);
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ipq9574_port_mac_clock_reset(i);
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if (!qca8084_swt_enb || (i != PORT0))
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ipq9574_port_mac_clock_reset(i);
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if (i == aquantia_port[0] || i == aquantia_port[1] ||
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phy_info[i]->phy_type == QCA8084_PHY_TYPE)
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((phy_info[i]->phy_type == QCA8084_PHY_TYPE) && (!qca8084_swt_enb))) {
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ipq9574_uxsgmii_speed_set(i, mac_speed, duplex, status);
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}
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else if (qca8084_swt_enb && (phy_info[i]->phy_type == QCA8084_PHY_TYPE))
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ipq_qca8084_link_update(phy_addr);
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else if ((i == sfp_port[0] || i == sfp_port[1]) && sgmii_fiber == 0)
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ipq9574_10g_r_speed_set(i, status);
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else
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@ -1831,10 +1848,11 @@ int ipq9574_edma_hw_init(struct ipq9574_edma_hw *ehw)
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return 0;
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}
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void get_phy_address(int offset)
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void get_phy_address(int offset, phy_info_t * phy_info[])
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{
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int phy_type;
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int phy_address;
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int forced_speed, forced_duplex;
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int i;
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for (i = 0; i < IPQ9574_PHY_MAX; i++)
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@ -1846,7 +1864,13 @@ void get_phy_address(int offset)
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offset, "phy_address", 0);
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phy_type = fdtdec_get_uint(gd->fdt_blob,
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offset, "phy_type", 0);
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forced_speed = fdtdec_get_uint(gd->fdt_blob,
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offset, "forced-speed", 0);
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forced_duplex = fdtdec_get_uint(gd->fdt_blob,
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offset, "forced-duplex", 0);
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phy_info[i]->phy_address = phy_address;
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phy_info[i]->forced_speed = forced_speed;
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phy_info[i]->forced_duplex = forced_duplex;
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phy_info[i++]->phy_type = phy_type;
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}
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}
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@ -1870,6 +1894,7 @@ int ipq9574_edma_init(void *edma_board_cfg)
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#ifdef CONFIG_QCA8084_PHY
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static int qca8084_init_done = 0;
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int phy_type;
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int qca8084_gpio, swt_node = -1, clk[4] = {0};
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#endif
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int node, phy_addr, mode, phy_node = -1, res = -1;
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int aquantia_port[2] = {-1, -1}, aquantia_port_cnt = -1;
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@ -1892,9 +1917,22 @@ int ipq9574_edma_init(void *edma_board_cfg)
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}
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}
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#ifdef CONFIG_QCA8084_PHY
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qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node, "qca8084_switch_enable", 0);
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qca8084_gpio = fdtdec_get_uint(gd->fdt_blob, node, "qca808x_gpio", 0);
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if (qca8084_swt_enb) {
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if (qca8084_gpio)
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ipq_qca8084_switch_hw_reset(qca8084_gpio);
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}
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swt_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/qca8084_swt_info");
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if (swt_node >= 0)
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get_phy_address(swt_node, swt_info);
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#endif
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phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
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if (phy_node >= 0)
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get_phy_address(phy_node);
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get_phy_address(phy_node, phy_info);
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mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1);
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if (mode < 0) {
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@ -2084,6 +2122,37 @@ int ipq9574_edma_init(void *edma_board_cfg)
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if (ret)
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goto init_failed;
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/** QCA8084 switch specific configurations */
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if (qca8084_swt_enb) {
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/** Force speed alder 1st port for QCA8084 switch mode */
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switch (swt_info[0]->forced_speed) {
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case FAL_SPEED_1000:
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case FAL_SPEED_2500:
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clk[0] = 0x201;
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clk[1] = 0x0;
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clk[2] = 0x301;
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clk[3] = 0x0;
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pr_debug("Force speed Alder 1st PORT for QCA8084 switch mode \n");
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ipq9574_speed_clock_set(PORT0, clk);
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/** Force Link-speed: 1000M
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* Force Link-status: enable */
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ipq9574_pqsgmii_speed_set(PORT0, 0x2, 0x0);
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break;
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default:
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printf("Error: Unsupported speed configuraiton for QCA8084 switch \n");
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break;
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}
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ret = ipq_qca8084_hw_init(swt_info, swt_node);
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if (ret < 0) {
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printf("Error: ipq_qca8084_hw_init failed \n");
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goto init_failed;
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}
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}
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eth_register(dev[i]);
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}
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@ -831,6 +831,7 @@ void ppe_port_mux_mac_type_set(int port_id, int mode)
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case EPORT_WRAPPER_SGMII0_RGMII4:
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case EPORT_WRAPPER_SGMII_PLUS:
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case EPORT_WRAPPER_SGMII_FIBER:
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case EPORT_WRAPPER_SGMII_CHANNEL0:
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port_type = PORT_GMAC_TYPE;
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break;
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case EPORT_WRAPPER_USXGMII:
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@ -235,10 +235,30 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
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mdelay(100);
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}
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void ppe_uniphy_set_forceMode(void)
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{
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uint32_t reg_value;
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reg_value = readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
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reg_value |= UNIPHY_FORCE_SPEED_25M;
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writel(reg_value, PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
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}
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static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
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{
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writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
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if (uniphy_index == 0) {
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writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
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ppe_uniphy_set_forceMode();
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writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
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} else {
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writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
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}
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writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
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@ -254,7 +274,12 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
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ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
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mdelay(100);
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if (uniphy_index == 1) {
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if (uniphy_index == 0) {
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writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR);
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writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4);
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writel(0x0, NSS_CC_PORT1_RX_CBCR);
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writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4);
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} else if (uniphy_index == 1) {
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writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
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writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
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writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
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@ -280,7 +305,11 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
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break;
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case EPORT_WRAPPER_SGMII_PLUS:
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writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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if (uniphy_index == 0)
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writel(0x20, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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+ PPE_UNIPHY_MODE_CONTROL);
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else
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writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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+ PPE_UNIPHY_MODE_CONTROL);
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break;
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@ -304,7 +333,12 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
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}
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mdelay(100);
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if (uniphy_index == 1) {
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if (uniphy_index == 0) {
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writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR);
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writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4);
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writel(0x1, NSS_CC_PORT1_RX_CBCR);
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writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4);
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} else if (uniphy_index == 1) {
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writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
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writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
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writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
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@ -41,6 +41,12 @@
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#define UNIPHY_MISC2_REG_VALUE 0x70
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#define UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET 0x21c
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#define UNIPHY_MISC_SRC_PHY_MODE 0xa882
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#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480
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#define UNIPHY_FORCE_SPEED_25M (1 << 3)
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#define UNIPHY_PLL_RESET_REG_OFFSET 0x780
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#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf
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#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff
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