diff --git a/board/qca/arm/ipq807x/ipq807x.c b/board/qca/arm/ipq807x/ipq807x.c
index c0b2a54b90..0aa168470d 100644
--- a/board/qca/arm/ipq807x/ipq807x.c
+++ b/board/qca/arm/ipq807x/ipq807x.c
@@ -42,7 +42,7 @@ const char *del_node[] = {"uboot",
 			  "sbl",
 			  NULL};
 const add_node_t add_node[] = {{}};
-
+static int pci_initialised;
 struct dumpinfo_t dumpinfo[] = {
 	{ "EBICS0.BIN", 0x40000000, 0x10000000, 0 },
 	{ "CODERAM.BIN", 0x00200000, 0x00024000, 0 },
@@ -274,6 +274,35 @@ void board_nand_init(void)
 	}
 }
 
+static void pcie_clock_init(int id)
+{
+
+	/* Enable PCIE CLKS */
+	if (id == 0) {
+		writel(0x2, GCC_PCIE0_AUX_CMD_RCGR);
+		writel(0x107, GCC_PCIE0_AXI_CFG_RCGR);
+		writel(0x1, GCC_PCIE0_AXI_CMD_RCGR);
+		mdelay(100);
+		writel(0x2, GCC_PCIE0_AXI_CMD_RCGR);
+		writel(0x20000001, GCC_PCIE0_AHB_CBCR);
+		writel(0x4FF1, GCC_PCIE0_AXI_M_CBCR);
+		writel(0x20004FF1, GCC_PCIE0_AXI_S_CBCR);
+		writel(0x1, GCC_PCIE0_AUX_CBCR);
+		writel(0x80004FF1, GCC_PCIE0_PIPE_CBCR);
+		writel(0x2, GCC_PCIE1_AUX_CMD_RCGR);
+		writel(0x107, GCC_PCIE1_AXI_CFG_RCGR);
+		writel(0x1, GCC_PCIE1_AXI_CMD_RCGR);
+		mdelay(100);
+		writel(0x2, GCC_PCIE1_AXI_CMD_RCGR);
+		writel(0x20000001, GCC_PCIE1_AHB_CBCR);
+		writel(0x4FF1, GCC_PCIE1_AXI_M_CBCR);
+		writel(0x20004FF1, GCC_PCIE1_AXI_S_CBCR);
+		writel(0x1, GCC_PCIE1_AUX_CBCR);
+		writel(0x80004FF1, GCC_PCIE1_PIPE_CBCR);
+		pci_initialised = 1;
+	}
+}
+
 void board_pci_init(int id)
 {
 	int node, gpio_node;
@@ -289,6 +318,7 @@ void board_pci_init(int id)
 	if (gpio_node >= 0)
 		qca_gpio_init(gpio_node);
 
+	pcie_clock_init(id);
 	return ;
 }
 
diff --git a/board/qca/arm/ipq807x/ipq807x.h b/board/qca/arm/ipq807x/ipq807x.h
index dcb9e2e40f..6c23dab235 100644
--- a/board/qca/arm/ipq807x/ipq807x.h
+++ b/board/qca/arm/ipq807x/ipq807x.h
@@ -30,6 +30,24 @@
 #define GCC_SDCC1_APPS_D	0x1842014
 #define GCC_BLSP1_UART1_APPS_CBCR       0x0180203c
 
+#define GCC_PCIE0_AXI_M_CBCR	0x01875008
+#define GCC_PCIE0_AXI_S_CBCR	0x0187500C
+#define GCC_PCIE0_AHB_CBCR	0x01875010
+#define GCC_PCIE0_AUX_CBCR	0x01875014
+#define GCC_PCIE0_PIPE_CBCR	0x01875018
+#define GCC_PCIE0_AUX_CMD_RCGR	0x01875020
+#define GCC_PCIE0_AXI_CMD_RCGR	0x01875050
+#define GCC_PCIE0_AXI_CFG_RCGR	0x01875058
+
+#define GCC_PCIE1_AXI_M_CBCR	0x01876008
+#define GCC_PCIE1_AXI_S_CBCR	0x0187600C
+#define GCC_PCIE1_AHB_CBCR	0x01876010
+#define GCC_PCIE1_AUX_CBCR	0x01876014
+#define GCC_PCIE1_PIPE_CBCR	0x01876018
+#define GCC_PCIE1_AUX_CMD_RCGR	0x01876020
+#define GCC_PCIE1_AXI_CMD_RCGR	0x01876050
+#define GCC_PCIE1_AXI_CFG_RCGR	0x01876058
+
 #define KERNEL_AUTH_CMD		0x13
 
 typedef enum {