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u-boot: drivers: net: Update edma config for ipq6018

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Change-Id: I23f198474cdc73f7d2fb0c0dcc328bd080b6799a
Signed-off-by: speriaka <speriaka@codeaurora.org>
This commit is contained in:
speriaka 2019-05-24 10:33:00 +05:30 • committed by Gerrit - the friendly Code Review server
parent a11373f000
commit 31277e6448
3 changed files with 15 additions and 65 deletions
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25
arch/arm/include/asm/arch-ipq6018/edma_regs.h
View file

@ -26,9 +26,6 @@
#define IPQ6018_EDMA_REG_MAS_CTRL 0x0
#define IPQ6018_EDMA_REG_PORT_CTRL 0x4
#define IPQ6018_EDMA_REG_VLAN_CTRL 0x8
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_0 0xc
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_1 0x10
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_2 0x14
#define IPQ6018_EDMA_REG_RXDESC2FILL_MAP_0 0x18
#define IPQ6018_EDMA_REG_RXDESC2FILL_MAP_1 0x1c
#define IPQ6018_EDMA_REG_TXQ_CTRL 0x20
@ -54,17 +51,17 @@
#define IPQ6018_EDMA_REG_TXDESC_CONS_IDX(n) (0x1008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_RING_SIZE(n) (0x100c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_CTRL(n) (0x1010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BA(n) (0x19000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_PROD_IDX(n) (0x19004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CONS_IDX(n) (0x19008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_RING_SIZE(n) (0x1900c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_UGT_THRE(n) (0x19010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CTRL(n) (0x19014 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BPC(n) (0x19018 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_STAT(n) (0x21000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_MASK(n) (0x21004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_MOD_TIMER(n) (0x21008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_CTRL(n) (0x2100c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BA(n) (0x79000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_PROD_IDX(n) (0x79004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CONS_IDX(n) (0x79008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_RING_SIZE(n) (0x7900c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_UGT_THRE(n) (0x79010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CTRL(n) (0x79014 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BPC(n) (0x79018 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_STAT(n) (0x91000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_MASK(n) (0x91004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_MOD_TIMER(n) (0x91008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_CTRL(n) (0x9100c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_BA(n) (0x29000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_PROD_IDX(n) (0x29004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_CONS_IDX(n) (0x29008 + (0x1000 * n))

46
drivers/net/ipq6018/ipq6018_edma.c
View file

@ -1585,42 +1585,6 @@ int ipq6018_edma_hw_init(struct ipq6018_edma_hw *ehw)
ipq6018_edma_configure_rings(ehw);
/*
* Clear the TXDESC2CMPL_MAP_xx reg before setting up
* the mapping. This register holds TXDESC to TXFILL ring
* mapping.
*/
ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_0, 0);
ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_1, 0);
ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_2, 0);
desc_index = ehw->txcmpl_ring_start;
/*
* 3 registers to hold the completion mapping for total 24
* TX desc rings (0-9,10-19 and rest). In each entry 3 bits hold
* the mapping for a particular TX desc ring.
*/
for (i = ehw->txdesc_ring_start;
i < ehw->txdesc_ring_end; i++) {
if (i >= 0 && i <= 9)
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_0;
else if (i >= 10 && i <= 19)
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_1;
else
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_2;
pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n",
i, desc_index);
data = ipq6018_edma_reg_read(reg);
data |= (desc_index & 0x7) << ((i % 10) * 3);
ipq6018_edma_reg_write(reg, data);
desc_index++;
if (desc_index == ehw->txcmpl_ring_end)
desc_index = ehw->txcmpl_ring_start;
}
/*
* Set PPE QID to EDMA Rx ring mapping.
* When coming up use only queue 0.
@ -1673,16 +1637,6 @@ int ipq6018_edma_hw_init(struct ipq6018_edma_hw *ehw)
pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n",
ipq6018_edma_reg_read(reg));
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_0;
pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n",
ipq6018_edma_reg_read(reg));
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_1;
pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n",
ipq6018_edma_reg_read(reg));
reg = IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_2;
pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n",
ipq6018_edma_reg_read(reg));
/*
* Enable MISC interrupt
*/

9
drivers/net/ipq6018/ipq6018_edma.h
View file

@ -19,7 +19,7 @@
#define __IPQ6018_EDMA__
#define IPQ6018_NSS_DP_START_PHY_PORT 1
#define IPQ6018_NSS_DP_MAX_PHY_PORTS 6
#define IPQ6018_NSS_DP_MAX_PHY_PORTS 5
#define IPQ6018_EDMA_BUF_SIZE 2000
#define IPQ6018_EDMA_DEVICE_NODE_NAME "edma"
@ -36,7 +36,7 @@
#define IPQ6018_EDMA_MAX_GMACS IPQ6018_NSS_DP_MAX_PHY_PORTS
#define IPQ6018_EDMA_TX_BUF_SIZE (1540 + IPQ6018_EDMA_TX_PREHDR_SIZE)
#define IPQ6018_EDMA_MAX_TXCMPL_RINGS 8 /* Max TxCmpl rings */
#define IPQ6018_EDMA_MAX_TXCMPL_RINGS 24 /* Max TxCmpl rings */
#define IPQ6018_EDMA_MAX_RXDESC_RINGS 16 /* Max RxDesc rings */
#define IPQ6018_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */
#define IPQ6018_EDMA_MAX_TXDESC_RINGS 24 /* Max TxDesc rings */
@ -52,14 +52,13 @@
#define IPQ6018_EDMA_TX_QUEUE 1
#define IPQ6018_EDMA_RX_QUEUE 1
//#define IPQ6018_EDMA_TX_DESC_RING_START 23
#define IPQ6018_EDMA_TX_DESC_RING_START 0
#define IPQ6018_EDMA_TX_DESC_RING_NOS 1
#define IPQ6018_EDMA_TX_DESC_RING_SIZE \
(IPQ6018_EDMA_TX_DESC_RING_START + IPQ6018_EDMA_TX_DESC_RING_NOS)
#define IPQ6018_EDMA_TX_CMPL_RING_START 7
#define IPQ6018_EDMA_TX_CMPL_RING_NOS 1
#define IPQ6018_EDMA_TX_CMPL_RING_START 0
#define IPQ6018_EDMA_TX_CMPL_RING_NOS 8
#define IPQ6018_EDMA_TX_CMPL_RING_SIZE \
(IPQ6018_EDMA_TX_CMPL_RING_START + IPQ6018_EDMA_TX_CMPL_RING_NOS)