From 48fa91a9a81bd5c1ba617e5aae068be986285dcf Mon Sep 17 00:00:00 2001
From: Timple Raj M <quic_timple@quicinc.com>
Date: Mon, 24 Apr 2023 11:23:47 +0530
Subject: [PATCH] arm: dts: ipq5332: Updated the PCIe configuration of
 AP-MI01.3

In AP-MI01.3 RDP, PCIe0 and PCIe1 are enabled in single
lane configuration

Change-Id: I5592d50ebb425a92ad536142573d09cdd60206b2
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
---
 arch/arm/dts/ipq5332-mi01.3.dts | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/ipq5332-mi01.3.dts b/arch/arm/dts/ipq5332-mi01.3.dts
index 20c44e85b7..2b9c9b26bb 100644
--- a/arch/arm/dts/ipq5332-mi01.3.dts
+++ b/arch/arm/dts/ipq5332-mi01.3.dts
@@ -25,6 +25,8 @@
 		mmc = "/sdhci@7804000";
 		usb0 = "/xhci@8a00000";
 		i2c0 = "/i2c@78B6000";
+		pci0 = "/pci@20000000";
+		pci1 = "/pci@18000000";
 	};
 
 	serial@78AF000 {
@@ -179,6 +181,34 @@
 		};
 	};
 
+	pci0: pci@20000000 {
+		status = "ok";
+		perst_gpio = <38>;
+		lane = <1>;
+		pci_gpio {
+			pci_rst {
+				gpio = <38>;
+				pull = <GPIO_PULL_UP>;
+				oe = <GPIO_OE_ENABLE>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	pci1: pci@18000000 {
+		status = "ok";
+		perst_gpio = <47>;
+		lane = <1>;
+		pci_gpio {
+			pci_rst {
+				gpio = <47>;
+				pull = <GPIO_PULL_UP>;
+				oe = <GPIO_OE_ENABLE>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
 	ess-switch {
 		switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
 		switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;