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AU_LINUX_QSDK_DATE_4.4_TARGET_ALL.11.5.0.7945

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Merge AU_LINUX_QSDK_DATE_4.4_TARGET_ALL.11.5.0.7945 on remote branch

Change-Id: Ie89d38142698928c30ebd2f4dc4fb0b749924242
Signed-off-by: Linux Build Service Account <lnxbuild@localhost>
This commit is contained in:
Linux Build Service Account 2021-12-01 03:36:53 -07:00
commit 2ef8bb7013
12 changed files with 114 additions and 124 deletions
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4
arch/arm/dts/ipq5018-soc.dtsi
View file

@ -37,6 +37,10 @@
compatible = "qcom,spi-qup-v2.7.0";
wr_pipe_0 = <4>;
rd_pipe_0 = <5>;
wr_pipe_1 = <6>;
rd_pipe_1 = <7>;
wr_pipe_2 = <8>;
rd_pipe_2 = <9>;
status = "ok";
spi_gpio {
blsp0_spi_clk {

11
arch/arm/dts/ipq6018-soc.dtsi
View file

@ -81,6 +81,17 @@
compatible = "qcom,spi-qup-v2.7.0";
wr_pipe_0 = <12>;
rd_pipe_0 = <13>;
wr_pipe_1 = <14>;
rd_pipe_1 = <15>;
wr_pipe_2 = <16>;
rd_pipe_2 = <17>;
wr_pipe_3 = <18>;
rd_pipe_3 = <19>;
wr_pipe_4 = <20>;
rd_pipe_4 = <21>;
wr_pipe_5 = <22>;
rd_pipe_5 = <23>;
spi_gpio {
gpio1 {
gpio = <38>;

11
arch/arm/dts/ipq807x-soc.dtsi
View file

@ -61,6 +61,17 @@
compatible = "qcom,spi-qup-v2.7.0";
wr_pipe_0 = <12>;
rd_pipe_0 = <13>;
wr_pipe_1 = <14>;
rd_pipe_1 = <15>;
wr_pipe_2 = <16>;
rd_pipe_2 = <17>;
wr_pipe_3 = <18>;
rd_pipe_3 = <19>;
wr_pipe_4 = <20>;
rd_pipe_4 = <21>;
wr_pipe_5 = <22>;
rd_pipe_5 = <23>;
};
nand: nand-controller@79B0000 {

10
arch/arm/dts/ipq9574-soc.dtsi
View file

@ -88,6 +88,16 @@
compatible = "qcom,spi-qup-v2.7.0";
wr_pipe_0 = <12>;
rd_pipe_0 = <13>;
wr_pipe_1 = <14>;
rd_pipe_1 = <15>;
wr_pipe_2 = <16>;
rd_pipe_2 = <17>;
wr_pipe_3 = <18>;
rd_pipe_3 = <19>;
wr_pipe_4 = <20>;
rd_pipe_4 = <21>;
wr_pipe_5 = <22>;
rd_pipe_5 = <23>;
status = "ok";
spi_gpio {
};

22
common/usb.c
View file

@ -46,6 +46,8 @@
#define TRANSCEND_USB_VENDOR_ID 0x8564
#define TRANSCEND_USB_PRODUCT_ID 0x1000
#define SP_USB_VENDOR_ID 0x058f
#define SP_USB_PRODUCT_ID 0x6387
static int asynch_allowed;
char usb_started; /* flag for the started/stopped USB status */
@ -1091,18 +1093,22 @@ int usb_select_config(struct usb_device *dev)
le16_to_cpus(&dev->descriptor.idProduct);
le16_to_cpus(&dev->descriptor.bcdDevice);
/*The Transcend device fails for get configuration length. Adding
delay about 10 micro secs to fix this.*/
if (dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID)
/*The Transcend and Silicon-power devices fails for get configuration length.
Adding delay about 10 micro secs to fix this.*/
if ((dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID) ||
(dev->descriptor.idVendor == SP_USB_VENDOR_ID &&
dev->descriptor.idProduct == SP_USB_PRODUCT_ID))
udelay(10);
/* only support for one config for now */
err = usb_get_configuration_len(dev, 0);
/*The Transcend device fails for get configuration number. Adding
delay about 10 micro secs to fix this.*/
if (dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID)
/*The Transcend and Silicon-power devices fails for get configuration number.
Adding delay about 10 micro secs to fix this.*/
if ((dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID) ||
(dev->descriptor.idVendor == SP_USB_VENDOR_ID &&
dev->descriptor.idProduct == SP_USB_PRODUCT_ID))
udelay(10);
if (err >= 0) {

18
drivers/spi/qca_qup_spi_bam.c
View file

@ -40,8 +40,8 @@
DECLARE_GLOBAL_DATA_PTR;
static unsigned int read_pipe[NO_OF_QUPS];
static unsigned int write_pipe[NO_OF_QUPS];
static unsigned int read_pipe[CONFIG_IPQ_MAX_BLSP_QUPS];
static unsigned int write_pipe[CONFIG_IPQ_MAX_BLSP_QUPS];
static unsigned char qup_pipe_initialized = 0;
static int check_bit_state(uint32_t reg_addr, int bit_num, int val,
@ -177,7 +177,7 @@ static void qup_pipe_init(void)
qup_pipe_initialized = 1;
node = fdt_path_offset(gd->fdt_blob, "/spi");
if (node >= 0) {
for(i = 0; i < NO_OF_QUPS; i++) {
for(i = 0; i < CONFIG_IPQ_MAX_BLSP_QUPS; i++) {
snprintf(rd_pipe_name, sizeof(rd_pipe_name),
"rd_pipe_%01d", i);
@ -352,19 +352,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
memset(ds, 0, sizeof(struct ipq_spi_slave));
/*
* QCA BLSP supports SPI Flash
* on different BLSP0 and BLSP1
* on different BLSP 0 to CONFIG_IPQ_MAX_BLSP_QUPS-1
* with different number of chip selects (CS, channels):
*/
if ((bus > BLSP1_SPI)
|| ((bus == BLSP0_SPI) && (cs > 2))
|| ((bus == BLSP1_SPI) && (cs > 0))) {
if (bus >= CONFIG_IPQ_MAX_BLSP_QUPS){
printf("SPI error: unsupported bus %d "
"(Supported busses 0,1 and 2) or chipselect\n", bus);
"Supported busses 0 to %d\n", bus, CONFIG_IPQ_MAX_BLSP_QUPS-1);
goto err;
}
ds->slave.bus = bus;
ds->slave.cs = cs;
BLSP_SPI_REGISTERS(spi_reg[bus]);
ds->regs = &spi_reg[bus];
/* TODO For different clock frequency */
@ -384,7 +384,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
/* DMA mode */
ds->use_dma = CONFIG_QUP_SPI_USE_DMA;
if (ds->slave.cs == 1 &&
if (ds->slave.cs >= 1 &&
cs_is_valid(ds->slave.bus, ds->slave.cs)) {
/* GPIO Configuration for SPI NAND */
blsp_pin_config(ds->slave.bus, ds->slave.cs);

148
drivers/spi/qca_qup_spi_bam.h
View file

@ -31,73 +31,51 @@
#ifndef _IPQ_SPI_BAM_H_
#define _IPQ_SPI_BAM_H_
#define QUP0_BASE 0x78b5000
#define QUP1_BASE 0x78b6000
#define QUP_BASE 0x78b5000
#define BLSP0_BAM_BASE 0x7884000
#define BLSP0_QUP_REG_BASE (QUP0_BASE + 0x00000000)
#define BLSP1_QUP_REG_BASE (QUP1_BASE + 0x00000000)
#define BLSP_QUP_REG_BASE(p) (QUP_BASE + (p*0x1000) )
#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
#define BLSP1_SPI_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000300)
#define BLSP_SPI_CONFIG_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000300)
#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
#define BLSP1_SPI_IO_CONTROL_REG (BLSP1_QUP_REG_BASE + 0x00000304)
#define BLSP_SPI_IO_CONTROL_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000304)
#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
#define BLSP1_SPI_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x00000308)
#define BLSP_SPI_ERROR_FLAGS_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000308)
#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
#define BLSP1_SPI_DEASSERT_WAIT_REG (BLSP1_QUP_REG_BASE + 0x00000310)
#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
#define BLSP1_SPI_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x0000030c)
#define BLSP_SPI_DEASSERT_WAIT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000310)
#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
#define BLSP1_QUP_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000000)
#define BLSP_SPI_ERROR_FLAGS_EN_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000030c)
#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
#define BLSP1_QUP_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x0000001c)
#define BLSP_QUP_CONFIG_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000000)
#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
#define BLSP1_QUP_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x00000020)
#define BLSP_QUP_ERROR_FLAGS_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000001c)
#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
#define BLSP1_QUP_OPERATIONAL_MASK (BLSP1_QUP_REG_BASE + 0x00000028)
#define BLSP_QUP_ERROR_FLAGS_EN_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000020)
#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
#define BLSP1_QUP_OPERATIONAL_REG (BLSP1_QUP_REG_BASE + 0x00000018)
#define BLSP_QUP_OPERATIONAL_MASK(p) (BLSP_QUP_REG_BASE(p) + 0x00000028)
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
#define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
#define BLSP_QUP_OPERATIONAL_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000018)
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
#define BLSP_QUP_IO_MODES_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000008)
#define BLSP_QUP_STATE_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000004)
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
#define BLSP1_QUP_INPUT_FIFOc_REG(c) \
(BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
#define BLSP_QUP_INPUT_FIFOc_REG(p, c) \
(BLSP_QUP_REG_BASE(p) + 0x00000218 + 4 * (c))
#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
#define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
(BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
#define BLSP_QUP_OUTPUT_FIFOc_REG(p, c) \
(BLSP_QUP_REG_BASE(p) + 0x00000110 + 4 * (c))
#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
#define BLSP1_QUP_MX_INPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000200)
#define BLSP_QUP_MX_INPUT_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000200)
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
#define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
#define BLSP_QUP_MX_OUTPUT_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000100)
#define BLSP0_QUP_MX_READ_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000208)
#define BLSP1_QUP_MX_READ_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000208)
#define BLSP_QUP_MX_READ_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000208)
#define BLSP0_QUP_MX_WRITE_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000150)
#define BLSP1_QUP_MX_WRITE_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000150)
#define BLSP_QUP_MX_WRITE_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000150)
#define BLSP_QUP_SW_RESET_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000000C)
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
#define QUP_STATE_VALID_BIT 2
#define QUP_STATE_VALID 1
@ -191,52 +169,28 @@ struct blsp_spi {
unsigned int qup_deassert_wait;
};
static const struct blsp_spi spi_reg[] = {
/* BLSP0 registers for SPI interface */
{
BLSP0_SPI_CONFIG_REG,
BLSP0_SPI_IO_CONTROL_REG,
BLSP0_SPI_ERROR_FLAGS_REG,
BLSP0_SPI_ERROR_FLAGS_EN_REG,
BLSP0_QUP_CONFIG_REG,
BLSP0_QUP_ERROR_FLAGS_REG,
BLSP0_QUP_ERROR_FLAGS_EN_REG,
BLSP0_QUP_OPERATIONAL_REG,
BLSP0_QUP_IO_MODES_REG,
BLSP0_QUP_STATE_REG,
BLSP0_QUP_INPUT_FIFOc_REG(0),
BLSP0_QUP_OUTPUT_FIFOc_REG(0),
BLSP0_QUP_MX_INPUT_COUNT_REG,
BLSP0_QUP_MX_OUTPUT_COUNT_REG,
BLSP0_QUP_MX_READ_COUNT_REG,
BLSP0_QUP_MX_WRITE_COUNT_REG,
BLSP0_QUP_SW_RESET_REG,
BLSP0_QUP_OPERATIONAL_MASK,
BLSP0_SPI_DEASSERT_WAIT_REG,
},
/* BLSP1 registers for SPI interface */
{
BLSP1_SPI_CONFIG_REG,
BLSP1_SPI_IO_CONTROL_REG,
BLSP1_SPI_ERROR_FLAGS_REG,
BLSP1_SPI_ERROR_FLAGS_EN_REG,
BLSP1_QUP_CONFIG_REG,
BLSP1_QUP_ERROR_FLAGS_REG,
BLSP1_QUP_ERROR_FLAGS_EN_REG,
BLSP1_QUP_OPERATIONAL_REG,
BLSP1_QUP_IO_MODES_REG,
BLSP1_QUP_STATE_REG,
BLSP1_QUP_INPUT_FIFOc_REG(0),
BLSP1_QUP_OUTPUT_FIFOc_REG(0),
BLSP1_QUP_MX_INPUT_COUNT_REG,
BLSP1_QUP_MX_OUTPUT_COUNT_REG,
BLSP1_QUP_MX_READ_COUNT_REG,
BLSP1_QUP_MX_WRITE_COUNT_REG,
BLSP1_QUP_SW_RESET_REG,
BLSP1_QUP_OPERATIONAL_MASK,
BLSP1_SPI_DEASSERT_WAIT_REG,
},
};
struct blsp_spi spi_reg[CONFIG_IPQ_MAX_BLSP_QUPS];
#define BLSP_SPI_REGISTERS(x) \
x.spi_config = BLSP_SPI_CONFIG_REG(bus);\
x.io_control = BLSP_SPI_IO_CONTROL_REG(bus);\
x.error_flags = BLSP_SPI_ERROR_FLAGS_REG(bus);\
x.error_flags_en = BLSP_SPI_ERROR_FLAGS_EN_REG(bus);\
x.qup_config = BLSP_QUP_CONFIG_REG(bus);\
x.qup_error_flags = BLSP_QUP_ERROR_FLAGS_REG(bus);\
x.qup_error_flags_en = BLSP_QUP_ERROR_FLAGS_EN_REG(bus);\
x.qup_operational = BLSP_QUP_OPERATIONAL_REG(bus);\
x.qup_io_modes = BLSP_QUP_IO_MODES_REG(bus);\
x.qup_state = BLSP_QUP_STATE_REG(bus);\
x.qup_input_fifo = BLSP_QUP_INPUT_FIFOc_REG(bus, 0);\
x.qup_output_fifo = BLSP_QUP_OUTPUT_FIFOc_REG(bus, 0);\
x.qup_mx_input_count = BLSP_QUP_MX_INPUT_COUNT_REG(bus);\
x.qup_mx_output_count = BLSP_QUP_MX_OUTPUT_COUNT_REG(bus);\
x.qup_mx_read_count = BLSP_QUP_MX_READ_COUNT_REG(bus);\
x.qup_mx_write_count = BLSP_QUP_MX_WRITE_COUNT_REG(bus);\
x.qup_sw_reset = BLSP_QUP_SW_RESET_REG(bus);\
x.qup_op_mask = BLSP_QUP_OPERATIONAL_MASK(bus);\
x.qup_deassert_wait = BLSP_SPI_DEASSERT_WAIT_REG(bus);\
#define SUCCESS 0
#define FAILURE 1
@ -268,14 +222,6 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
#define DATA_CONSUMER_PIPE_INDEX 0
#define DATA_PRODUCER_PIPE_INDEX 1
/* QUP0 BAM pipe numbers */
#define QUP0_DATA_CONSUMER_PIPE 12
#define QUP0_DATA_PRODUCER_PIPE 13
/* QUP1 BAM pipe numbers */
#define QUP1_DATA_CONSUMER_PIPE 6
#define QUP1_DATA_PRODUCER_PIPE 7
/* QUP0 BAM pipe groups */
#define QUP0_DATA_PRODUCER_PIPE_GRP 0
#define QUP0_DATA_CONSUMER_PIPE_GRP 0
@ -284,8 +230,6 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
#define QUP1_DATA_PRODUCER_PIPE_GRP 0
#define QUP1_DATA_CONSUMER_PIPE_GRP 0
#define NO_OF_QUPS 2
/* QUP EE */
#define QUP_SPI_EE 0

1
include/configs/ipq40xx.h
View file

@ -199,6 +199,7 @@ typedef struct {
#define CONFIG_SYS_MAX_NAND_DEVICE (CONFIG_IPQ_MAX_NAND_DEVICE + \
CONFIG_IPQ_MAX_SPI_DEVICE)
#define CONFIG_IPQ_MAX_BLSP_QUPS 2
#define CONFIG_IPQ_MAX_SPI_DEVICE 2
#define CONFIG_IPQ_MAX_NAND_DEVICE 1

1
include/configs/ipq5018.h
View file

@ -294,6 +294,7 @@ extern loff_t board_env_size;
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
#define CONFIG_IPQ_MAX_BLSP_QUPS 3
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1

2
include/configs/ipq6018.h
View file

@ -248,7 +248,7 @@ extern loff_t board_env_size;
CONFIG_IPQ_MAX_SPI_DEVICE
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX

1
include/configs/ipq807x.h
View file

@ -214,6 +214,7 @@ extern loff_t board_env_size;
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1

1
include/configs/ipq9574.h
View file

@ -220,6 +220,7 @@ extern loff_t board_env_size;
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1