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ipq807x: Added USB de-initialization functions

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Change-Id: Ia6877dfd96a65c2808cc67baa1eaa53afb924e80
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
This commit is contained in:
Vasudevan Murugesan 2017-06-30 12:10:34 +05:30 • committed by Gerrit - the friendly Code Review server
parent 69c3fa2774
commit 2e6fe13ebc
4 changed files with 111 additions and 20 deletions
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10
board/qca/arm/common/board_init.c
View file

@ -44,6 +44,16 @@ int ipq_board_usb_init(void)
{
return 0;
}
__weak
void board_usb_deinit(int id)
{
return 0;
}
__weak
void board_pci_deinit(void)
{
return 0;
}
int board_init(void)
{

23
board/qca/arm/common/cmd_bootqca.c
View file

@ -41,6 +41,7 @@ static qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
int ipq_fs_on_nand ;
extern int nand_env_device;
extern qca_mmc mmc_host;
extern void board_usb_deinit(int id);
#ifdef CONFIG_QCA_MMC
static qca_mmc *host = &mmc_host;
@ -346,7 +347,7 @@ int config_select(unsigned int addr, char *rcmd, int rcmd_size)
static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
char runcmd[256];
int ret;
int ret,i;
unsigned int request;
#ifdef CONFIG_QCA_MMC
block_dev_desc_t *blk_dev;
@ -481,6 +482,11 @@ static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const a
#endif
board_pci_deinit();
#ifdef CONFIG_USB_XHCI_IPQ
for (i=0; i<CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
board_usb_deinit(i);
}
#endif
ret = config_select(request, runcmd, sizeof(runcmd));
@ -490,6 +496,9 @@ static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const a
if (ret < 0 || run_command(runcmd, 0) != CMD_RET_SUCCESS) {
#ifdef CONFIG_QCA_MMC
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_USB_XHCI_IPQ
ipq_board_usb_init();
#endif
dcache_disable();
return CMD_RET_FAILURE;
@ -503,7 +512,7 @@ static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const a
static int do_boot_unsignedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int ret;
int ret,i;
char runcmd[256];
#ifdef CONFIG_QCA_MMC
block_dev_desc_t *blk_dev;
@ -615,6 +624,12 @@ static int do_boot_unsignedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const
board_pci_deinit();
#ifdef CONFIG_USB_XHCI_IPQ
for (i=0; i<CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
board_usb_deinit(i);
}
#endif
setenv("mtdids", mtdids);
ret = genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR);
@ -641,7 +656,11 @@ static int do_boot_unsignedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const
}
}
if (ret < 0 || run_command(runcmd, 0) != CMD_RET_SUCCESS) {
#ifdef CONFIG_USB_XHCI_IPQ
ipq_board_usb_init();
#endif
dcache_disable();
return CMD_RET_FAILURE;
}

97
board/qca/arm/ipq807x/ipq807x.c
View file

@ -383,6 +383,70 @@ void board_pci_deinit()
return ;
}
void board_usb_deinit(int id)
{
void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
void __iomem *usb_phy_bcr, *usb_gen_cfg, *usb_guctl, *phy_base;
if (id == 0) {
boot_clk_ctl = GCC_USB_0_BOOT_CLOCK_CTL;
usb_bcr = GCC_USB0_BCR;
qusb2_phy_bcr = GCC_QUSB2_0_PHY_BCR;
usb_phy_bcr = GCC_USB0_PHY_BCR;
usb_gen_cfg = USB30_1_GENERAL_CFG;
usb_guctl = USB30_1_GUCTL;
phy_base = USB30_PHY_1_QUSB2PHY_BASE;
}
else if (id == 1) {
boot_clk_ctl = GCC_USB_1_BOOT_CLOCK_CTL;
usb_bcr = GCC_USB1_BCR;
qusb2_phy_bcr = GCC_QUSB2_1_PHY_BCR;
usb_phy_bcr = GCC_USB1_PHY_BCR;
usb_gen_cfg = USB30_2_GENERAL_CFG;
usb_guctl = USB30_2_GUCTL;
phy_base = USB30_PHY_2_QUSB2PHY_BASE;
}
else {
return;
}
//Enable USB2 PHY Power down
setbits_le32(phy_base+0xB4, 0x1);
if (id == 0) {
writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
writel(0xcff0, GCC_USB0_MASTER_CBCR);
writel(0, GCC_SYS_NOC_USB0_AXI_CBCR);
writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
writel(0, GCC_USB0_SLEEP_CBCR);
writel(0, GCC_USB0_MOCK_UTMI_CBCR);
writel(0, GCC_USB0_AUX_CBCR);
}
else if (id == 1) {
writel(0x8000, GCC_USB1_PHY_CFG_AHB_CBCR);
writel(0xcff0, GCC_USB1_MASTER_CBCR);
writel(0, GCC_SYS_NOC_USB1_AXI_CBCR);
writel(0, GCC_SNOC_BUS_TIMEOUT3_AHB_CBCR);
writel(0, GCC_USB1_SLEEP_CBCR);
writel(0, GCC_USB1_MOCK_UTMI_CBCR);
writel(0, GCC_USB1_AUX_CBCR);
}
//GCC_QUSB2_0_PHY_BCR
setbits_le32(qusb2_phy_bcr, 0x1);
mdelay(10);
clrbits_le32(qusb2_phy_bcr, 0x1);
//GCC_USB0_PHY_BCR
setbits_le32(usb_phy_bcr, 0x1);
mdelay(10);
clrbits_le32(usb_phy_bcr, 0x1);
//GCC Reset USB0 BCR
setbits_le32(usb_bcr, 0x1);
mdelay(10);
clrbits_le32(usb_bcr, 0x1);
}
static void usb_clock_init(int id)
{
if (id == 0) {
@ -391,9 +455,9 @@ static void usb_clock_init(int id)
writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
writel(0x10b, GCC_USB0_MASTER_CFG_RCGR);
writel(0x1, GCC_USB0_MASTER_CMD_RCGR);
writel(1, GCC_SYS_NOC_USB0_AXI_CBCR);
writel(0xcff1, GCC_USB0_MASTER_CBCR);
writel(1, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
writel(1, GCC_SYS_NOC_USB0_AXI_CBCR);
writel(1, GCC_USB0_SLEEP_CBCR);
writel(0x210b, GCC_USB0_MOCK_UTMI_CFG_RCGR);
writel(0x1, GCC_USB0_MOCK_UTMI_M);
@ -407,12 +471,12 @@ static void usb_clock_init(int id)
else if (id == 1) {
writel(0x222000, GCC_USB1_GDSCR);
writel(0, GCC_SYS_NOC_USB1_AXI_CBCR);
writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
writel(0, GCC_SNOC_BUS_TIMEOUT3_AHB_CBCR);
writel(0x10b, GCC_USB1_MASTER_CFG_RCGR);
writel(0x1, GCC_USB1_MASTER_CMD_RCGR);
writel(0xcff1, GCC_USB1_MASTER_CBCR);
writel(1, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
writel(1, GCC_SYS_NOC_USB1_AXI_CBCR);
writel(0xcff1, GCC_USB1_MASTER_CBCR);
writel(1, GCC_SNOC_BUS_TIMEOUT3_AHB_CBCR);
writel(1, GCC_USB1_SLEEP_CBCR);
writel(0x210b, GCC_USB1_MOCK_UTMI_CFG_RCGR);
writel(0x1, GCC_USB1_MOCK_UTMI_M);
@ -485,37 +549,34 @@ static void usb_init_phy(int index)
//12. Delay 100us
mdelay(10);
//13. Enable USB Boot Clock
setbits_le32(boot_clk_ctl, 0x1);
//14. Enable PIPE_UTMI_CLK_DIS
//13. Enable PIPE_UTMI_CLK_DIS
setbits_le32(usb_gen_cfg, 0x100);
//15. Delay 100us
//14. Delay 100us
mdelay(10);
//16. Enable PIPE_UTMI_CLK_SEL
//15. Enable PIPE_UTMI_CLK_SEL
setbits_le32(usb_gen_cfg, 0x1);
//17. Delay 100us
//16. Delay 100us
mdelay(10);
//18. Enable PIPE3_PHYSTATUS_SW
//17. Enable PIPE3_PHYSTATUS_SW
setbits_le32(usb_gen_cfg, 0x8);
//19. Delay 100us
//18. Delay 100us
mdelay(10);
//20. Disable PIPE_UTMI_CLK_DIS
//19. Disable PIPE_UTMI_CLK_DIS
clrbits_le32(usb_gen_cfg, 0x100);
//21. Config user control register
//20. Config user control register
writel(0x0c80c010, usb_guctl);
//22. Enable USB2 PHY Power down
//21. Enable USB2 PHY Power down
setbits_le32(phy_base+0xB4, 0x1);
//23. PHY Config Sequence
//22. PHY Config Sequence
out_8(phy_base+0x80, 0xF8);
out_8(phy_base+0x84, 0x83);
out_8(phy_base+0x88, 0x83);
@ -529,7 +590,7 @@ static void usb_init_phy(int index)
out_8(phy_base+0x1C, 0x9F);
out_8(phy_base+0x04, 0x80);
//24. Disable USB2 PHY Power down
//23. Disable USB2 PHY Power down
clrbits_le32(phy_base+0xB4, 0x1);
}

1
board/qca/arm/ipq807x/ipq807x.h
View file

@ -80,6 +80,7 @@
#define GCC_USB1_GDSCR 0x183F078
#define GCC_SYS_NOC_USB1_AXI_CBCR 0x1826044
#define GCC_SNOC_BUS_TIMEOUT3_AHB_CBCR 0x01847014
#define GCC_USB1_MASTER_CFG_RCGR 0x183F010
#define GCC_USB1_MASTER_CMD_RCGR 0x183F00C
#define GCC_USB1_MASTER_CBCR 0x183F000