From c3c600f1209287f958020478cd50d88843964209 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Mon, 13 Feb 2023 19:38:16 +0530 Subject: [PATCH] board: qca: arm: ipq5332: Fix to reduce the noise in High Speed TX Eye This patch adds the XCFG configuration in HS PHY sequence to reduce the noise in High Speed TX Eye Change-Id: Iac430aa8bbd9ccc9a84c164578a1b6e35b3771f8 Signed-off-by: Timple Raj M --- board/qca/arm/ipq5332/ipq5332.c | 17 +++++++++++++++++ board/qca/arm/ipq5332/ipq5332.h | 10 ++++++++++ 2 files changed, 27 insertions(+) diff --git a/board/qca/arm/ipq5332/ipq5332.c b/board/qca/arm/ipq5332/ipq5332.c index d6fd1ab5cc..ea2136e537 100644 --- a/board/qca/arm/ipq5332/ipq5332.c +++ b/board/qca/arm/ipq5332/ipq5332.c @@ -727,6 +727,23 @@ static void usb_init_hsphy(void __iomem *phybase, int ssphy) writel(XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, phybase + USB2PHY_USB_PHY_M31_XCFGI_11); + /* Adjust HSTX slew rate to 565 ps*/ + /* Adjust PLL lock Time counter for release clock to 35uA */ + /* Adjust Manual control ODT value to 38.02 Ohm */ + writel(HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | + ODT_VALUE_38_02_OHM, phybase + USB2PHY_USB_PHY_M31_XCFGI_4); + + /* + * Enable to always turn on USB 2.0 TX driver + * when system is in USB 2.0 HS mode + */ + writel(USB2_0_TX_ENABLE, phybase + USB2PHY_USB_PHY_M31_XCFGI_1); + + /* Adjust Manual control ODT value to 45.02 Ohm */ + /* Adjust HSTX Pre-emphasis level to 0.55mA */ + writel(ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA, + phybase + USB2PHY_USB_PHY_M31_XCFGI_5); + udelay(10); writel(0, phybase + USB_PHY_UTMI_CTRL5); diff --git a/board/qca/arm/ipq5332/ipq5332.h b/board/qca/arm/ipq5332/ipq5332.h index ce2981890f..ec6d5bf6df 100644 --- a/board/qca/arm/ipq5332/ipq5332.h +++ b/board/qca/arm/ipq5332/ipq5332.h @@ -84,8 +84,18 @@ extern const add_node_t add_fdt_node[]; #define USB_PHY_HS_PHY_CTRL_COMMON0 0x54 #define USB_PHY_REFCLK_CTRL 0xA0 #define USB_PHY_HS_PHY_CTRL2 0x64 +#define USB2PHY_USB_PHY_M31_XCFGI_1 0xBC +#define USB2PHY_USB_PHY_M31_XCFGI_4 0xC8 +#define USB2PHY_USB_PHY_M31_XCFGI_5 0xCC #define USB2PHY_USB_PHY_M31_XCFGI_11 0xE4 +#define USB2_0_TX_ENABLE BIT(2) +#define HSTX_SLEW_RATE_565PS 3 +#define PLL_CHARGING_PUMP_CURRENT_35UA (3 << 3) +#define ODT_VALUE_38_02_OHM (3 << 6) +#define ODT_VALUE_45_02_OHM BIT(2) +#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA (1) + #define UTMI_PHY_OVERRIDE_EN BIT(1) #define SLEEPM BIT(1) #define POR_EN BIT(1)