From 29c2f25f72baf44fe5364d673fc36f7cc58dc451 Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Mon, 2 Aug 2021 10:56:26 +0530 Subject: [PATCH] drivers: net: ipq9574: Clean up drivers This patch does the following: 1) Removes unused macros and functions 2) Updates EDMA Reset address and assert/de-assert values 3) Updates Port5 and Port6 address in uniphy clock config 4) Reduces delay to 500 us in usxgmii uniphy mode set 5) Disable clearing of mac counters Change-Id: I7cc9b20bbd4f2367d9f405ae2e5652d6236476a9 Signed-off-by: Selvam Sathappan Periakaruppan --- board/qca/arm/ipq9574/ipq9574.h | 6 ++-- drivers/net/ipq9574/ipq9574_edma.c | 26 ++---------------- drivers/net/ipq9574/ipq9574_edma.h | 16 ----------- drivers/net/ipq9574/ipq9574_ppe.c | 2 +- drivers/net/ipq9574/ipq9574_ppe.h | 1 - drivers/net/ipq9574/ipq9574_uniphy.c | 41 ++++++++++++++-------------- 6 files changed, 25 insertions(+), 67 deletions(-) diff --git a/board/qca/arm/ipq9574/ipq9574.h b/board/qca/arm/ipq9574/ipq9574.h index 41b9758c03..f22d596473 100644 --- a/board/qca/arm/ipq9574/ipq9574.h +++ b/board/qca/arm/ipq9574/ipq9574.h @@ -26,10 +26,8 @@ /* * EDMA HW ASSERT and DEASSERT values */ -#define GCC_NSS_PPE_RESET 0x01868014 -#define GCC_EDMA_HW_RESET_ASSERT 0x300000 -#define GCC_EDMA_HW_RESET_DEASSERT 0x0 -#define GCC_NSS_PORT1_RX_MISC 0x01868400 +#define NSS_CC_EDMA_HW_RESET_ASSERT 0x18000 +#define NSS_CC_EDMA_HW_RESET_DEASSERT 0x0 #define NSS_CC_PORT1_RX_CMD_RCGR 0x39B28110 #define NSS_CC_PORT5_RX_CMD_RCGR 0x39B28170 #define NSS_CC_PORT5_TX_CMD_RCGR 0x39B2817C diff --git a/drivers/net/ipq9574/ipq9574_edma.c b/drivers/net/ipq9574/ipq9574_edma.c index 7ad67c5b7e..a9d2625c7c 100644 --- a/drivers/net/ipq9574/ipq9574_edma.c +++ b/drivers/net/ipq9574/ipq9574_edma.c @@ -50,11 +50,7 @@ phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0}; int sgmii_mode[2] = {0}; #ifndef CONFIG_IPQ9574_RUMI -extern void qca8075_ess_reset(void); -extern void psgmii_self_test(void); -extern void clear_self_test_config(void); extern int ipq_sw_mdio_init(const char *); -extern void ipq_qca8075_dump_phy_regs(u32); extern int ipq_mdio_read(int mii_id, int regnum, ushort *data); extern void ipq_qca8075_phy_map_ops(struct phy_ops **ops); extern int ipq_qca8075_phy_init(struct phy_ops **ops); @@ -72,24 +68,6 @@ static int tftp_acl_our_port; */ static u32 ipq9574_edma_hw_addr; -void ipq9574_edma_dump_data(uchar *data, int len) -{ - int i; - - if (data == NULL) - return; - - pr_info("data address = 0x%x, len = %d \n", (unsigned int)data, len); - - for (i = 0; i < len; i++) { - if ((i % 16) == 0) - printf("\n"); - pr_info("%02x ", (unsigned int)data[i]); - } - - pr_info("\n\n"); -} - /* * ipq9574_edma_reg_read() * Read EDMA register @@ -1658,9 +1636,9 @@ static void ipq9574_edma_configure_rings(struct ipq9574_edma_hw *ehw) */ void ipq9574_edma_hw_reset(void) { - writel(GCC_EDMA_HW_RESET_ASSERT, GCC_NSS_PPE_RESET); + writel(NSS_CC_EDMA_HW_RESET_ASSERT, NSS_CC_PPE_RESET_ADDR); udelay(100); - writel(GCC_EDMA_HW_RESET_DEASSERT, GCC_NSS_PPE_RESET); + writel(NSS_CC_EDMA_HW_RESET_DEASSERT, NSS_CC_PPE_RESET_ADDR); udelay(100); } diff --git a/drivers/net/ipq9574/ipq9574_edma.h b/drivers/net/ipq9574/ipq9574_edma.h index 3accdb891c..c7fdfa7c35 100644 --- a/drivers/net/ipq9574/ipq9574_edma.h +++ b/drivers/net/ipq9574/ipq9574_edma.h @@ -84,24 +84,8 @@ #define IPQ9574_EDMA_RX_FILL_RING_SIZE \ (IPQ9574_EDMA_RX_FILL_RING_START + IPQ9574_EDMA_RX_FILL_RING_NOS) -#define IPQ9574_EDMA_TX_IMR_NORMAL_MASK 1 -#define IPQ9574_EDMA_RX_IMR_NORMAL_MASK 1 -#define IPQ9574_EDMA_INTR_CLEAR_TYPE 0 -#define IPQ9574_EDMA_INTR_SW_IDX_W_TYPE 0 -#define IPQ9574_EDMA_RSS_TYPE_NONE 0x1 - #define NETDEV_TX_BUSY 1 -#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x0009878c -#define PSGMIIPHY_PLL_VCO_VAL 0x2803 - -#define PSGMIIPHY_VCO_CALIBRATION_CTRL 0x0009809c -#define PSGMIIPHY_VCO_VAL 0x4ADA -#define PSGMIIPHY_VCO_RST_VAL 0xADA - -#define RGMII_TCSR_ESS_CFG 0x01953000 -#define ESS_RGMII_CTRL 0x0C000004 - /* * RxDesc descriptor */ diff --git a/drivers/net/ipq9574/ipq9574_ppe.c b/drivers/net/ipq9574/ipq9574_ppe.c index 7e9ba4c022..c13643700a 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.c +++ b/drivers/net/ipq9574/ipq9574_ppe.c @@ -475,7 +475,7 @@ void ipq9574_pqsgmii_speed_set(int port, int speed, int status) ppe_port_bridge_txmac_set(port + 1, status); ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed); ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73); - ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); } /* diff --git a/drivers/net/ipq9574/ipq9574_ppe.h b/drivers/net/ipq9574/ipq9574_ppe.h index d7b2aa078e..c91c367ad3 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.h +++ b/drivers/net/ipq9574/ipq9574_ppe.h @@ -31,7 +31,6 @@ #define PORT4 4 #define PORT5 5 #define PORT6 6 -#define PORT7 7 #define IPQ9574_PORT5_MUX_PCS_UNIPHY0 0x0 #define IPQ9574_PORT5_MUX_PCS_UNIPHY1 0x1 diff --git a/drivers/net/ipq9574/ipq9574_uniphy.c b/drivers/net/ipq9574/ipq9574_uniphy.c index 2b487e713c..7ca36cc730 100644 --- a/drivers/net/ipq9574/ipq9574_uniphy.c +++ b/drivers/net/ipq9574/ipq9574_uniphy.c @@ -23,6 +23,7 @@ #include #include "ipq9574_edma.h" #include "ipq9574_uniphy.h" +#include "ipq9574_ppe.h" #include #include "ipq_phy.h" @@ -243,15 +244,15 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode) ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); if (uniphy_index == 1) { - writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 3*0x8); - writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + 3*0x8); - writel(0x0, NSS_CC_PORT1_RX_CBCR + 3*0x8); - writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + 3*0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); } else if (uniphy_index == 2) { - writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 4*0x8); - writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + 4*8); - writel(0x0, NSS_CC_PORT1_RX_CBCR + 4*0x8); - writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + 4*0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8); } switch (mode) { @@ -292,15 +293,15 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode) } if (uniphy_index == 1) { - writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 3*0x8); - writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + 3*0x8); - writel(0x1, NSS_CC_PORT1_RX_CBCR + 3*0x8); - writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + 3*0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); } else if (uniphy_index == 2) { - writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 4*0x8); - writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + 4*8); - writel(0x1, NSS_CC_PORT1_RX_CBCR + 4*0x8); - writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + 4*0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8); } ppe_uniphy_calibration(uniphy_index); @@ -386,20 +387,18 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index) if (uniphy_index == 0) { ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); - mdelay(100); + udelay(500); ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); } else if (uniphy_index == 1) { ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); - mdelay(100); + udelay(500); ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); } else { ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); - mdelay(100); + udelay(500); ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); } - mdelay(100); - ppe_uniphy_calibration(uniphy_index); if (uniphy_index == 0)