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powerpc/corenet: CPC1 speculation disable

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In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Dave Liu 2013-11-28 14:58:08 +08:00 • committed by York Sun
parent f44483b57c
commit 24936ed1c9
1 changed files with 4 additions and 0 deletions
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4
arch/powerpc/cpu/mpc85xx/start.S
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@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
erratum_set_ccsr 0x10f00 0x415e5000
#endif
erratum_set_ccsr 0x11f00 0x415e5000
/* Make temp mapping uncacheable again, if it was initially */