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board: sama5d2_ptc_ek: adjust the smc timings of nand

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To fix the issue of write the rootfs.ubi, adjust the smc timings
configuration of the nand controller.

Based on original work by Wenyou Yang

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This commit is contained in:
Eugen Hristev 2018-04-24 10:43:53 +03:00 • committed by Tom Rini
parent 8ee54672df
commit 23dd6015ce
1 changed files with 2 additions and 2 deletions
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4
board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
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@ -33,10 +33,10 @@ static void board_nand_hw_init(void)
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
&smc->cs[3].setup); &smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse); &smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle); &smc->cs[3].cycle);
writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |