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Merge "arm: dts: Add Ethernet support for db-cp01"

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Linux Build Service Account 2019-06-07 15:35:31 -07:00 • committed by Gerrit - the friendly Code Review server
commit 1f10c52b39
6 changed files with 218 additions and 103 deletions
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32
arch/arm/dts/ipq6018-db-cp01.dts
View file

@ -26,4 +26,36 @@
usb0 = "/xhci@8a00000";
usb1 = "/xhci@7000000";
};
ess-switch {
switch_mac_mode = <PORT_WRAPPER_PSGMII>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
napa_gpio = <77>;
napa_gpio_cnt = <1>;
malibu_gpio = <75>;
malibu_gpio_cnt = <1>;
mdc_mdio_gpio = <64 65>;
port_phyinfo {
port@0 {
phy_address = <0>;
phy_type = <MALIBU_PHY_TYPE>;
};
port@1 {
phy_address = <1>;
phy_type = <MALIBU_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <MALIBU_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <MALIBU_PHY_TYPE>;
};
port@4 {
phy_address = <24>;
phy_type = <QCA8081_PHY_TYPE>;
};
};
};
};

100
drivers/net/ipq6018/ipq6018_edma.c
View file

@ -853,17 +853,17 @@ static void ipq6018_edma_disable_intr(struct ipq6018_edma_hw *ehw)
static void set_sgmii_mode(int port_id, int sg_mode)
{
if (port_id == 4)
if (port_id == 3)
sgmii_mode[0] = sg_mode;
else if (port_id == 5)
else if (port_id == 4)
sgmii_mode[1] = sg_mode;
}
static int get_sgmii_mode(int port_id)
{
if (port_id == 4)
if (port_id == 3)
return sgmii_mode[0];
else if (port_id == 5)
else if (port_id == 4)
return sgmii_mode[1];
else
return -1;
@ -946,43 +946,41 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
switch (speed) {
case FAL_SPEED_10:
mac_speed = 0x0;
if (i == aquantia_port) {
printf("10M speed not supported\n");
ppe_port_bridge_txmac_set(i + 1, status);
continue;
}
mac_speed = 0x0;
speed_clock1 = 0x109;
speed_clock2 = 0x9;
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
if (phy_node >= 0) {
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE)
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
set_sgmii_mode(i, 1);
if (i == 4)
speed_clock1 = 0x309;
}
}
break;
case FAL_SPEED_100:
mac_speed = 0x1;
if (i == aquantia_port) {
if (i == 4)
speed_clock1 = 0x309;
else
speed_clock1 = 0x109;
} else if (i == port_8033)
if (i == aquantia_port && i == 4)
speed_clock1 = 0x309;
else
speed_clock1 = 0x109;
else
speed_clock1 = 0x101;
if (i == port_8033)
speed_clock2 = 0x0;
else
speed_clock2 = 0x4;
speed_clock2 = 0x0;
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
if (phy_node >= 0) {
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE)
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
set_sgmii_mode(i, 1);
if (i == 4)
speed_clock1 = 0x309;
}
}
break;
case FAL_SPEED_1000:
@ -999,49 +997,39 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
if (phy_node >= 0) {
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE)
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
set_sgmii_mode(i, 1);
if ((phy_info[i]->phy_type == QCA8081_PHY_TYPE) && (i == 4))
speed_clock1 = 0x301;
if ((phy_info[i]->phy_type == QCA8081_PHY_TYPE) && (i == 3))
speed_clock1 = 0x301;
if (i == 4)
speed_clock1 = 0x301;
}
}
break;
case FAL_SPEED_10000:
mac_speed = 0x3;
if (i == 4)
speed_clock1 = 0x301;
else
speed_clock1 = 0x101;
speed_clock2 = 0x0;
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
break;
case FAL_SPEED_2500:
if (phy_node >= 0) {
if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
mac_speed = 0x2;
if (i == 4 || i == 3)
speed_clock1 = 0x301;
else if (i == 5)
speed_clock1 = 0x101;
set_sgmii_mode(i, 0);
if (i == 4)
speed_clock1 = 0x301;
else if (i == 3)
speed_clock1 = 0x101;
speed_clock2 = 0x0;
}
if (phy_info[i]->phy_type == AQ_PHY_TYPE) {
} else if (phy_info[i]->phy_type == AQ_PHY_TYPE) {
mac_speed = 0x4;
if (i == 4) {
speed_clock1 = 0x301;
speed_clock2 = 0x3;
} else if (i == 5) {
} else if (i == 3) {
speed_clock1 = 0x107;
speed_clock2 = 0x0;
}
}
} else {
speed_clock1 = 0x107;
mac_speed = 0x4;
if (i == 4)
speed_clock1 = 0x307;
else
speed_clock1 = 0x107;
speed_clock2 = 0x0;
}
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
@ -1050,13 +1038,22 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
break;
case FAL_SPEED_5000:
mac_speed = 0x5;
if (i == 4) {
speed_clock1 = 0x301;
speed_clock2 = 0x1;
} else {
if (i == 4)
speed_clock1 = 0x303;
else
speed_clock1 = 0x103;
speed_clock2 = 0x0;
}
speed_clock2 = 0x0;
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
break;
case FAL_SPEED_10000:
mac_speed = 0x3;
if (i == 4)
speed_clock1 = 0x301;
else
speed_clock1 = 0x101;
speed_clock2 = 0x0;
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
@ -1073,8 +1070,8 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
ppe_port_bridge_txmac_set(i + 1, 1);
if (i == 4)
ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII0_RGMII4);
else if (i == 5)
ppe_uniphy_mode_set(0x2, PORT_WRAPPER_SGMII0_RGMII4);
else if (i == 3)
ppe_uniphy_mode_set(0x0, PORT_WRAPPER_SGMII0_RGMII4);
} else if (ret_sgmii_mode == 0) {
ppe_port_bridge_txmac_set(i + 1, 1);
@ -1085,6 +1082,7 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
}
}
}
ipq6018_speed_clock_set(i, speed_clock1, speed_clock2);
if (i == aquantia_port)
ipq6018_uxsgmii_speed_set(i, mac_speed, duplex, status);
else if (i == sfp_port)

54
drivers/net/ipq6018/ipq6018_ppe.c
View file

@ -173,12 +173,28 @@ static void ipq6018_gmac_port_enable(int port)
void ipq6018_speed_clock_set(int port, int speed_clock1, int speed_clock2)
{
int i;
uint32_t reg_value;
for (i = 0; i < 2; i++)
{
writel(speed_clock2, GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10);
writel(speed_clock1, GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10);
writel(0x1, GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10);
/* gcc port first clock divider */
reg_value = 0;
reg_value = readl(GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10);
reg_value &= ~0x71f;
reg_value |= speed_clock1;
writel(reg_value, GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10);
/* gcc port second clock divider */
reg_value = 0;
reg_value = readl(GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10);
reg_value &= ~0xf;
reg_value |= speed_clock2;
writel(reg_value, GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10);
/* update above clock configuration */
reg_value = 0;
reg_value = readl(GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10);
reg_value &= ~0x1;
reg_value |= 0x1;
writel(reg_value, GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10);
}
}
@ -309,10 +325,10 @@ void ipq6018_10g_r_speed_set(int port, int status)
uint32_t uniphy_index;
/* Setting the speed only for PORT5 and PORT6 */
if (port == (PORT5 - PPE_UNIPHY_INSTANCE1))
if (port == (PORT4 - PPE_UNIPHY_INSTANCE0))
uniphy_index = PPE_UNIPHY_INSTANCE0;
else if (port == (PORT5 - PPE_UNIPHY_INSTANCE0))
uniphy_index = PPE_UNIPHY_INSTANCE1;
else if (port == (PORT6 - PPE_UNIPHY_INSTANCE1))
uniphy_index = PPE_UNIPHY_INSTANCE2;
else
return;
@ -329,10 +345,10 @@ void ipq6018_uxsgmii_speed_set(int port, int speed, int duplex,
uint32_t uniphy_index;
/* Setting the speed only for PORT5 and PORT6 */
if (port == (PORT5 - PPE_UNIPHY_INSTANCE1))
if (port == (PORT4 - PPE_UNIPHY_INSTANCE0))
uniphy_index = PPE_UNIPHY_INSTANCE0;
else if (port == (PORT5 - PPE_UNIPHY_INSTANCE0))
uniphy_index = PPE_UNIPHY_INSTANCE1;
else if (port == (PORT6 - PPE_UNIPHY_INSTANCE1))
uniphy_index = PPE_UNIPHY_INSTANCE2;
else
return;
@ -1116,16 +1132,23 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
if (mode == PORT_WRAPPER_SGMII_PLUS) {
port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS;
port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS;
port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK;
} else if (mode == PORT_WRAPPER_PSGMII) {
if (fdtdec_get_int(gd->fdt_blob, nodeoff, "malibu2port_phy", 0))
if (fdtdec_get_int(gd->fdt_blob, nodeoff, "malibu2port_phy", 0)) {
port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
else
port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK;
} else {
port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_PSGMII;
port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK;
}
}
break;
case 5:
if (mode == PORT_WRAPPER_SGMII_PLUS)
if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4)
port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
else if (mode == PORT_WRAPPER_PSGMII)
port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
@ -1193,7 +1216,6 @@ void ipq6018_ppe_interface_mode_init(void)
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
ppe_port_mux_mac_type_set(3, mode0);
ppe_port_mux_mac_type_set(4, mode0);
ppe_port_mux_mac_type_set(5, mode1);
}
@ -1283,7 +1305,7 @@ void ipq6018_ppe_provision_init(void)
ipq6018_ppe_reg_write(0x060038, 0xc0);
#ifdef CONFIG_IPQ6018_BRIDGED_MODE
ipq6018_vsi_setup(2, 0x7f);
ipq6018_vsi_setup(2, 0x3f);
#else
ipq6018_vsi_setup(2, 0x03);
ipq6018_vsi_setup(3, 0x05);
@ -1296,7 +1318,7 @@ void ipq6018_ppe_provision_init(void)
ipq6018_ppe_reg_write(IPQ6018_PPE_STP_BASE + (0x4 * i), 0x3);
ipq6018_ppe_interface_mode_init();
/* Port 0-5 enable */
/* Port 0-4 enable */
for (i = 0; i < 5; i++) {
ipq6018_gmac_port_enable(i);
ppe_port_bridge_txmac_set(i + 1, 1);

13
drivers/net/ipq6018/ipq6018_ppe.h
View file

@ -32,17 +32,21 @@
#define IPQ6018_PPE_BASE_ADDR 0x3a000000
#define IPQ6018_PPE_REG_SIZE 0x1000000
#define PORT4 4
#define PORT5 5
#define PORT6 6
#define PORT_GMAC_TYPE 1
#define PORT_XGMAC_TYPE 2
struct port_mux_ctrl {
uint32_t port3_pcs_sel:2;
uint32_t port4_pcs_sel:2;
uint32_t port5_pcs_sel:2;
uint32_t port5_gmac_sel:1;
uint32_t _reserved0:25;
uint32_t pcs0_ch4_sel:1;
uint32_t pcs0_ch0_sel:1;
uint32_t _reserved0:23;
};
union port_mux_ctrl_u {
uint32_t val;
struct port_mux_ctrl bf;
@ -112,6 +116,11 @@ union ipo_action_u {
#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 1
#define CPPE_PORT5_GMAC_SEL_GMAC 0
#define CPPE_PORT5_GMAC_SEL_XGMAC 1
#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0
#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1
#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0
#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1
#define CPPE_DETECTION_PHY_FAILURE 0xFFFF
#define PORT_PHY_STATUS_ADDRESS 0x44
#define PORT_PHY_STATUS_PORT5_1_OFFSET 8

110
drivers/net/ipq6018/ipq6018_uniphy.c
View file

@ -90,18 +90,28 @@ static void ppe_gcc_uniphy_soft_reset(uint32_t uniphy_index)
uint32_t reg_value;
reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
if (uniphy_index == PPE_UNIPHY_INSTANCE0)
reg_value |= GCC_UNIPHY_PSGMII_SOFT_RESET;
else
reg_value = GCC_UNIPHY_USXGMII_SOFT_RESET;
reg_value |= GCC_UNIPHY_PSGMII_SOFT_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
udelay(500);
if (uniphy_index == PPE_UNIPHY_INSTANCE0)
reg_value &= ~GCC_UNIPHY_PSGMII_SOFT_RESET;
else
reg_value = GCC_UNIPHY_USXGMII_XPCS_RESET;
udelay(500);
reg_value &= ~GCC_UNIPHY_PSGMII_SOFT_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
}
static void ppe_gcc_uniphy_sgmii_soft_reset(uint32_t uniphy_index)
{
uint32_t reg_value;
reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
reg_value |= GCC_UNIPHY_SGMII_SOFT_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
udelay(500);
reg_value &= ~GCC_UNIPHY_SGMII_SOFT_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
}
@ -136,32 +146,42 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
reg_value = readl( PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
reg_value &= ~(UNIPHY_CH0_ATHR_CSCO_MODE_25M | UNIPHY_CH0_PSGMII_QSGMII);
if (uniphy_index == PPE_UNIPHY_INSTANCE0) {
reg_value &= ~UNIPHY_SG_MODE;
if (channel == 0) {
reg_value &= ~UNIPHY_CH1_CH0_SGMII;
reg_value &= ~UNIPHY_CH4_CH1_0_SGMII;
} else if (channel == 1) {
reg_value |= UNIPHY_CH1_CH0_SGMII;
reg_value &= ~UNIPHY_CH4_CH1_0_SGMII;
} else if (channel == 4) {
reg_value &= ~UNIPHY_CH1_CH0_SGMII;
reg_value |= UNIPHY_CH4_CH1_0_SGMII;
}
if (uniphy_index == 0) {
writel(0x0, GCC_UNIPHY0_PORT4_RX_CBCR);
writel(0x0, GCC_UNIPHY0_PORT4_TX_CBCR);
writel(0x0, GCC_NSS_PORT4_RX_CBCR);
writel(0x0, GCC_NSS_PORT4_TX_CBCR);
} else {
reg_value &= ~UNIPHY_SG_PLUS_MODE;
reg_value |= UNIPHY_SG_MODE;
writel(0x0, GCC_UNIPHY1_PORT5_RX_CBCR);
writel(0x0, GCC_UNIPHY1_PORT5_TX_CBCR);
writel(0x0, GCC_NSS_PORT5_RX_CBCR);
writel(0x0, GCC_NSS_PORT5_RX_CBCR);
}
writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
writel(0x420, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
ppe_gcc_uniphy_sgmii_soft_reset(uniphy_index);
if (uniphy_index == 0) {
writel(0x1, GCC_UNIPHY0_PORT4_RX_CBCR);
writel(0x1, GCC_UNIPHY0_PORT4_TX_CBCR);
writel(0x1, GCC_NSS_PORT4_RX_CBCR);
writel(0x1, GCC_NSS_PORT4_TX_CBCR);
} else {
writel(0x1, GCC_UNIPHY1_PORT5_RX_CBCR);
writel(0x1, GCC_UNIPHY1_PORT5_TX_CBCR);
writel(0x1, GCC_NSS_PORT5_RX_CBCR);
writel(0x1, GCC_NSS_PORT5_RX_CBCR);
}
ppe_uniphy_calibration(uniphy_index);
}
static void ppe_uniphy_sgmii_plus_mode_set(uint32_t uniphy_index)
{
uint32_t reg_value;
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
@ -171,9 +191,35 @@ static void ppe_uniphy_sgmii_plus_mode_set(uint32_t uniphy_index)
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x800, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
if (uniphy_index == 0) {
writel(0x0, GCC_UNIPHY0_PORT4_RX_CBCR);
writel(0x0, GCC_UNIPHY0_PORT4_TX_CBCR);
writel(0x0, GCC_NSS_PORT4_RX_CBCR);
writel(0x0, GCC_NSS_PORT4_TX_CBCR);
} else {
writel(0x0, GCC_UNIPHY1_PORT5_RX_CBCR);
writel(0x0, GCC_UNIPHY1_PORT5_TX_CBCR);
writel(0x0, GCC_NSS_PORT5_RX_CBCR);
writel(0x0, GCC_NSS_PORT5_RX_CBCR);
}
writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_sgmii_soft_reset(uniphy_index);
if (uniphy_index == 0) {
writel(0x1, GCC_UNIPHY0_PORT4_RX_CBCR);
writel(0x1, GCC_UNIPHY0_PORT4_TX_CBCR);
writel(0x1, GCC_NSS_PORT4_RX_CBCR);
writel(0x1, GCC_NSS_PORT4_TX_CBCR);
} else {
writel(0x1, GCC_UNIPHY1_PORT5_RX_CBCR);
writel(0x1, GCC_UNIPHY1_PORT5_TX_CBCR);
writel(0x1, GCC_NSS_PORT5_RX_CBCR);
writel(0x1, GCC_NSS_PORT5_RX_CBCR);
}
ppe_uniphy_calibration(uniphy_index);
}
@ -237,8 +283,6 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
reg_value &= ~SS5;
reg_value |= SS6 | SS13 | DUPLEX_MODE;
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
if (uniphy_index == PPE_UNIPHY_INSTANCE2);
ipq_mdio_write(0x7, ((1<<30) | (4<<16) | 0xc441), 8);
}
void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)

12
drivers/net/ipq6018/ipq6018_uniphy.h
View file

@ -13,7 +13,16 @@
*/
#define PPE_UNIPHY_INSTANCE0 0
#define PPE_UNIPHY_INSTANCE1 1
#define PPE_UNIPHY_INSTANCE2 2
#define GCC_UNIPHY1_PORT5_RX_CBCR 0x1856110
#define GCC_UNIPHY1_PORT5_TX_CBCR 0x1856114
#define GCC_NSS_PORT5_RX_CBCR 0x1868260
#define GCC_NSS_PORT5_TX_CBCR 0x1868264
#define GCC_UNIPHY0_PORT4_RX_CBCR 0x1856028
#define GCC_UNIPHY0_PORT4_TX_CBCR 0x185602C
#define GCC_NSS_PORT4_RX_CBCR 0x1868258
#define GCC_NSS_PORT4_TX_CBCR 0x186825C
#define GCC_UNIPHY0_MISC 0x01856004
#define GCC_UNIPHY_REG_INC 0x100
@ -25,6 +34,7 @@
#define GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2
#define GCC_UNIPHY_USXGMII_SOFT_RESET 0x36
#define GCC_UNIPHY_SGMII_SOFT_RESET 0x32
#define PPE_UNIPHY_BASE 0X07A00000
#define PPE_UNIPHY_REG_INC 0x10000