mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
drivers: net: ipq9574: Add support for qca8084
This patch adds support for qca8084 PHY based ports. Accordingly, updates the uniphy, ppe, clock configurations as required for qca8084 ports. Change-Id: I2e687c10adba579b0d47d8f5b529fe920b7d0d7c Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
This commit is contained in:
Selvam Sathappan Periakaruppan
Gerrit - the friendly Code Review server
parent
18d2b93ab3
commit
1c409bd8d6
5 changed files with 271 additions and 25 deletions
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@ -16,7 +16,6 @@
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**************************************************************************
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*/
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#include <common.h>
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#include <net.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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@ -49,6 +48,8 @@ uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
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phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0};
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int sgmii_mode[2] = {0};
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extern void ipq_phy_addr_fixup(void);
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extern void ipq_clock_init(void);
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extern int ipq_sw_mdio_init(const char *);
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extern int ipq_mdio_read(int mii_id, int regnum, ushort *data);
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extern void ipq9574_qca8075_phy_map_ops(struct phy_ops **ops);
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@ -58,6 +59,9 @@ extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id);
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extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id);
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extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id);
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extern int ipq_board_fw_download(unsigned int phy_addr);
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extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr);
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extern void qca8084_phy_uqxgmii_speed_fixup(uint32_t phy_addr, uint32_t qca8084_port_id,
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uint32_t status, fal_port_speed_t new_speed);
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static int tftp_acl_our_port;
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@ -936,6 +940,8 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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*/
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continue;
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}
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if(phy_info[i]->phy_type == UNUSED_PHY_TYPE)
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continue;
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if (i == sfp_port[0] || i == sfp_port[1]) {
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status = phy_status_get_from_ppe(i);
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duplex = FAL_FULL_DUPLEX;
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@ -1052,6 +1058,11 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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clk[0] = 0x409;
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clk[2] = 0x509;
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}
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} else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) {
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clk[0] = 0x213;
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clk[1] = 0x18;
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clk[2] = 0x313;
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clk[3] = 0x18;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1079,6 +1090,11 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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clk[0] = 0x409;
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clk[2] = 0x509;
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}
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} else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) {
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clk[0] = 0x204;
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clk[1] = 0x9;
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clk[2] = 0x304;
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clk[3] = 0x9;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1112,6 +1128,9 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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clk[0] = 0x401;
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clk[2] = 0x501;
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}
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} else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) {
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clk[0] = 0x204;
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clk[2] = 0x304;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1151,6 +1170,10 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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clk[0] = 0x201;
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clk[2] = 0x301;
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}
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} else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) {
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mac_speed = 0x4;
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clk[0] = 0x207;
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clk[2] = 0x307;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1236,9 +1259,14 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
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ipq9574_speed_clock_set(i, clk);
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if (phy_info[i]->phy_type == QCA8084_PHY_TYPE)
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qca8084_phy_uqxgmii_speed_fixup(phy_info[i]->phy_address, i + 1,
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status, curr_speed[i]);
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ipq9574_port_mac_clock_reset(i);
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if (i == aquantia_port[0] || i == aquantia_port[1])
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if (i == aquantia_port[0] || i == aquantia_port[1] ||
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phy_info[i]->phy_type == QCA8084_PHY_TYPE)
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ipq9574_uxsgmii_speed_set(i, mac_speed, duplex, status);
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else if ((i == sfp_port[0] || i == sfp_port[1]) && sgmii_fiber == 0)
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ipq9574_10g_r_speed_set(i, status);
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@ -1839,8 +1867,12 @@ int ipq9574_edma_init(void *edma_board_cfg)
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#ifdef CONFIG_IPQ9574_QCA8075_PHY
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static int sw_init_done = 0;
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#endif
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int node, phy_addr, aquantia_port[2] = {-1, -1}, aquantia_port_cnt = -1;
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int mode, phy_node = -1, res = -1;
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#ifdef CONFIG_QCA8084_PHY
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static int qca8084_init_done = 0;
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int phy_type;
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#endif
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int node, phy_addr, mode, phy_node = -1, res = -1;
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int aquantia_port[2] = {-1, -1}, aquantia_port_cnt = -1;
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/*
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* Init non cache buffer
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@ -1963,10 +1995,20 @@ int ipq9574_edma_init(void *edma_board_cfg)
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for (phy_id = 0; phy_id < IPQ9574_PHY_MAX; phy_id++) {
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if (phy_node >= 0) {
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phy_addr = phy_info[phy_id]->phy_address;
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#ifdef CONFIG_QCA8084_PHY
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phy_type = phy_info[phy_id]->phy_type;
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#endif
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} else {
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printf("Error:Phy addresses not configured in DT\n");
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goto init_failed;
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}
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#ifdef CONFIG_QCA8084_PHY
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if (phy_type == QCA8084_PHY_TYPE && !qca8084_init_done) {
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ipq_phy_addr_fixup();
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ipq_clock_init();
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qca8084_init_done = 1;
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}
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#endif
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phy_chip_id1 = ipq_mdio_read(phy_addr, QCA_PHY_ID1, NULL);
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phy_chip_id2 = ipq_mdio_read(phy_addr, QCA_PHY_ID2, NULL);
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@ -2008,6 +2050,11 @@ int ipq9574_edma_init(void *edma_board_cfg)
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ipq_qca8081_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr);
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break;
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#endif
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#ifdef CONFIG_QCA8084_PHY
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case QCA8084_PHY:
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ipq_qca8084_phy_hw_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr);
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break;
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#endif
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#ifdef CONFIG_IPQ9574_QCA_AQUANTIA_PHY
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case AQUANTIA_PHY_107:
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case AQUANTIA_PHY_109:
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@ -2026,7 +2073,7 @@ int ipq9574_edma_init(void *edma_board_cfg)
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#endif
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default:
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if (phy_info[phy_id]->phy_type != SFP_PHY_TYPE)
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printf("\nphy chip id: 0x%x id not matching for phy id: 0x%x with phy_type: 0x%x and phy address: 0x%x",
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pr_debug("\nphy chip id: 0x%x id not matching for phy id: 0x%x with phy_type: 0x%x and phy address: 0x%x",
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phy_chip_id, phy_id, phy_info[phy_id]->phy_type, phy_info[phy_id]->phy_address);
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break;
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}
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@ -428,7 +428,7 @@ void ppe_port_rxmac_status_set(uint32_t port)
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MAC_RX_CONFIGURATION_ADDRESS +
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value);
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reg_value |= 0x5ee00c0;
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reg_value |= 0x300000c0;
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reg_value |=RE;
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reg_value |=ACS;
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reg_value |=CST;
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@ -447,11 +447,11 @@ void ppe_mac_packet_filter_set(uint32_t port)
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pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port);
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ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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MAC_PACKET_FILTER_ADDRESS +
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(port * MAC_PACKET_FILTER_INC), 0x81);
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(port * MAC_PACKET_FILTER_INC), 0x80000081);
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pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS +
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(port * MAC_PACKET_FILTER_ADDRESS),
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0x81);
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0x80000081);
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}
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void ipq9574_10g_r_speed_set(int port, int status)
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@ -477,7 +477,7 @@ void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex,
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uniphy_index = PPE_UNIPHY_INSTANCE0;
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ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
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ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
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ppe_uniphy_usxgmii_speed_set(uniphy_index, port + 1, speed);
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ppe_xgmac_speed_set(port, speed);
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ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
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ppe_uniphy_usxgmii_port_reset(uniphy_index);
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@ -835,6 +835,7 @@ void ppe_port_mux_mac_type_set(int port_id, int mode)
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break;
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case EPORT_WRAPPER_USXGMII:
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case EPORT_WRAPPER_10GBASE_R:
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case EPORT_WRAPPER_UQXGMII:
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port_type = PORT_XGMAC_TYPE;
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break;
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default:
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@ -887,8 +888,10 @@ void ipq9574_ppe_interface_mode_init(void)
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ppe_port_mux_mac_type_set(PORT3, mode0);
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ppe_port_mux_mac_type_set(PORT4, mode0);
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if (mode1 == EPORT_WRAPPER_MAX) {
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ppe_port_mux_mac_type_set(PORT5, mode0);
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uniphy_port5_clock_source_set();
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if (mode0 != EPORT_WRAPPER_UQXGMII) {
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ppe_port_mux_mac_type_set(PORT5, mode0);
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uniphy_port5_clock_source_set();
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}
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} else if (is_uniphy_enabled(PPE_UNIPHY_INSTANCE1)) {
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ppe_port_mux_mac_type_set(PORT5, mode1);
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}
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@ -22,16 +22,8 @@
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#include <asm/io.h>
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#include <malloc.h>
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#include <phy.h>
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#include <net.h>
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#include <miiphy.h>
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#define PORT1 1
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#define PORT2 2
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#define PORT3 3
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#define PORT4 4
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#define PORT5 5
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#define PORT6 6
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#define IPQ9574_PORT5_MUX_PCS_UNIPHY0 0x0
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#define IPQ9574_PORT5_MUX_PCS_UNIPHY1 0x1
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@ -35,6 +35,7 @@ extern int ipq_mdio_write(int mii_id,
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern void ipq9574_qca8075_phy_serdes_reset(u32 phy_id);
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extern void qca8084_phy_interface_mode_set(void);
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void csr1_write(int phy_id, int addr, int value)
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{
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@ -373,6 +374,154 @@ static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
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ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false);
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}
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static void ppe_uniphy_uqxgmii_eee_set(uint32_t uniphy_index)
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{
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uint32_t reg_value = 0;
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/* configure eee related timer value */
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS);
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reg_value |= SIGN_BIT | MULT_FACT_100NS;
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csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS, reg_value);
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_TXTIMER_ADDRESS);
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reg_value |= UNIPHY_XPCS_TSL_TIMER | UNIPHY_XPCS_TLU_TIMER
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| UNIPHY_XPCS_TWL_TIMER;
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csr1_write(uniphy_index, VR_XS_PCS_EEE_TXTIMER_ADDRESS, reg_value);
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_RXTIMER_ADDRESS);
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reg_value |= UNIPHY_XPCS_100US_TIMER | UNIPHY_XPCS_TWR_TIMER;
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csr1_write(uniphy_index, VR_XS_PCS_EEE_RXTIMER_ADDRESS, reg_value);
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/* Transparent LPI mode and LPI pattern enable */
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL1_ADDRESS);
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reg_value |= TRN_LPI | TRN_RXLPI;
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csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL1_ADDRESS, reg_value);
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS);
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reg_value |= LRX_EN | LTX_EN;
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csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS, reg_value);
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}
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static void ppe_uniphy_uqxgmii_mode_set(uint32_t uniphy_index)
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{
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uint32_t reg_value = 0;
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writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
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/* reset uniphy */
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writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
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mdelay(500);
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writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
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(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
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mdelay(500);
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/* keep xpcs to reset status */
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if (uniphy_index == 0)
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ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
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else if (uniphy_index == 1)
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ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
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else
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ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
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mdelay(100);
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/* configure uniphy to usxgmii mode */
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writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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+ PPE_UNIPHY_MODE_CONTROL);
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reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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+ UNIPHYQP_USXG_OPITON1);
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reg_value |= GMII_SRC_SEL;
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writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
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+ UNIPHYQP_USXG_OPITON1);
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/* configure uniphy usxgmii gcc software reset */
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if (uniphy_index == 0) {
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ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
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mdelay(100);
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ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
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} else if (uniphy_index == 1) {
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ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
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mdelay(100);
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ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
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} else {
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ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
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mdelay(100);
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ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
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}
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mdelay(100);
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/* wait calibration done to uniphy */
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ppe_uniphy_calibration(uniphy_index);
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/* release xpcs reset status */
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if (uniphy_index == 0)
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ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false);
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else if (uniphy_index == 1)
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ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
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else
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ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false);
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mdelay(100);
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/* wait 10g base_r link up */
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ppe_uniphy_10g_r_linkup(uniphy_index);
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/* enable uniphy usxgmii */
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS);
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reg_value |= USXG_EN;
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csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value);
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/* set qxgmii mode */
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reg_value = csr1_read(uniphy_index, VR_XS_PCS_KR_CTRL_ADDRESS);
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reg_value |= USXG_MODE;
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csr1_write(uniphy_index, VR_XS_PCS_KR_CTRL_ADDRESS, reg_value);
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/* set AM interval mode */
|
||||
reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_STS_ADDRESS);
|
||||
reg_value |= AM_COUNT;
|
||||
csr1_write(uniphy_index, VR_XS_PCS_DIG_STS_ADDRESS, reg_value);
|
||||
|
||||
/* xpcs software reset */
|
||||
reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS);
|
||||
reg_value |= VR_RST;
|
||||
csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value);
|
||||
|
||||
/* enable uniphy autoneg complete interrupt and 10M/100M 8-bits MII width */
|
||||
reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS);
|
||||
reg_value |= MII_AN_INTR_EN;
|
||||
reg_value |= MII_CTRL;
|
||||
csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL1_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL2_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL3_ADDRESS, reg_value);
|
||||
|
||||
/* disable TICD */
|
||||
reg_value = csr1_read(uniphy_index, VR_XAUI_MODE_CTRL_ADDRESS);
|
||||
reg_value |= IPG_CHECK;
|
||||
csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL1_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL2_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL3_ADDRESS, reg_value);
|
||||
|
||||
/* enable uniphy autoneg ability and usxgmii 10g speed and full duplex */
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
|
||||
reg_value |= AN_ENABLE;
|
||||
reg_value &= ~SS5;
|
||||
reg_value |= SS6 | SS13 | DUPLEX_MODE;
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS, reg_value);
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS, reg_value);
|
||||
|
||||
/* enable uniphy eee transparent mode*/
|
||||
ppe_uniphy_uqxgmii_eee_set(uniphy_index);
|
||||
|
||||
#ifdef CONFIG_QCA8084_PHY
|
||||
/* phy interface mode configuration for qca8084 */
|
||||
qca8084_phy_interface_mode_set();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
||||
{
|
||||
|
|
@ -465,6 +614,10 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
|
|||
case EPORT_WRAPPER_10GBASE_R:
|
||||
ppe_uniphy_10g_r_mode_set(uniphy_index);
|
||||
break;
|
||||
case EPORT_WRAPPER_UQXGMII:
|
||||
case EPORT_WRAPPER_UQXGMII_3CHANNELS:
|
||||
ppe_uniphy_uqxgmii_mode_set(uniphy_index);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -488,11 +641,20 @@ void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index)
|
|||
csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value);
|
||||
}
|
||||
|
||||
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed)
|
||||
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, uint32_t port_id,
|
||||
int speed)
|
||||
{
|
||||
uint32_t reg_value = 0;
|
||||
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
|
||||
if (port_id == PORT2)
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS);
|
||||
else if (port_id == PORT3)
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS);
|
||||
else if (port_id == PORT4)
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS);
|
||||
else
|
||||
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
|
||||
|
||||
reg_value |= DUPLEX_MODE;
|
||||
|
||||
switch(speed) {
|
||||
|
|
@ -527,8 +689,15 @@ void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed)
|
|||
reg_value |=SS13;
|
||||
break;
|
||||
}
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
|
||||
|
||||
if (port_id == PORT2)
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS, reg_value);
|
||||
else if (port_id == PORT3)
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS, reg_value);
|
||||
else if (port_id == PORT4)
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS, reg_value);
|
||||
else
|
||||
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
|
||||
}
|
||||
|
||||
void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex)
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0)
|
||||
|
||||
#define UNIPHY_INSTANCE_LINK_DETECT 0x570
|
||||
#define UNIPHYQP_USXG_OPITON1 0x584
|
||||
|
||||
#define UNIPHY_MISC2_REG_OFFSET 0x218
|
||||
#define UNIPHY_MISC2_REG_SGMII_MODE 0x30
|
||||
|
|
@ -48,13 +49,47 @@
|
|||
#define UNIPHY_10GR_LINKUP 0x1
|
||||
|
||||
#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000
|
||||
#define USXG_EN (1 << 9)
|
||||
#define USRA_RST (1 << 10)
|
||||
#define VR_XS_PCS_EEE_MCTRL0_ADDRESS 0x38006
|
||||
#define VR_XS_PCS_KR_CTRL_ADDRESS 0x38007
|
||||
#define VR_XS_PCS_EEE_TXTIMER_ADDRESS 0x38008
|
||||
#define VR_XS_PCS_EEE_RXTIMER_ADDRESS 0x38009
|
||||
#define VR_XS_PCS_DIG_STS_ADDRESS 0x3800a
|
||||
#define VR_XS_PCS_EEE_MCTRL1_ADDRESS 0x3800b
|
||||
|
||||
#define SIGN_BIT (1 << 6)
|
||||
#define MULT_FACT_100NS (1 << 8)
|
||||
#define GMII_SRC_SEL (1 << 0)
|
||||
#define USXG_EN (1 << 9)
|
||||
#define USXG_MODE (5 << 10)
|
||||
#define USRA_RST (1 << 10)
|
||||
#define AM_COUNT (0x6018 << 0)
|
||||
#define VR_RST (1 << 15)
|
||||
#define UNIPHY_XPCS_TSL_TIMER (0xa << 0)
|
||||
#define UNIPHY_XPCS_TLU_TIMER (0x3 << 6)
|
||||
#define UNIPHY_XPCS_TWL_TIMER (0x16 << 8)
|
||||
#define UNIPHY_XPCS_100US_TIMER (0xc8 << 0)
|
||||
#define UNIPHY_XPCS_TWR_TIMER (0x1c << 8)
|
||||
#define TRN_LPI (1 << 0)
|
||||
#define TRN_RXLPI (1 << 8)
|
||||
#define LRX_EN (1 << 0)
|
||||
#define LTX_EN (1 << 1)
|
||||
|
||||
#define VR_MII_AN_CTRL_CHANNEL1_ADDRESS 0x1a8001
|
||||
#define VR_MII_AN_CTRL_CHANNEL2_ADDRESS 0x1b8001
|
||||
#define VR_MII_AN_CTRL_CHANNEL3_ADDRESS 0x1c8001
|
||||
#define VR_MII_AN_CTRL_ADDRESS 0x1f8001
|
||||
#define MII_AN_INTR_EN (1 << 0)
|
||||
#define MII_CTRL (1 << 8)
|
||||
|
||||
#define VR_XAUI_MODE_CTRL_CHANNEL1_ADDRESS 0x1a8004
|
||||
#define VR_XAUI_MODE_CTRL_CHANNEL2_ADDRESS 0x1b8004
|
||||
#define VR_XAUI_MODE_CTRL_CHANNEL3_ADDRESS 0x1c8004
|
||||
#define VR_XAUI_MODE_CTRL_ADDRESS 0x1f8004
|
||||
#define IPG_CHECK 0x1
|
||||
|
||||
#define SR_MII_CTRL_CHANNEL1_ADDRESS 0x1a0000
|
||||
#define SR_MII_CTRL_CHANNEL2_ADDRESS 0x1b0000
|
||||
#define SR_MII_CTRL_CHANNEL3_ADDRESS 0x1c0000
|
||||
#define SR_MII_CTRL_ADDRESS 0x1f0000
|
||||
#define AN_ENABLE (1 << 12)
|
||||
#define SS5 (1 << 5)
|
||||
|
|
@ -78,5 +113,5 @@ enum uniphy_reset_type {
|
|||
void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode);
|
||||
void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index);
|
||||
void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex);
|
||||
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed);
|
||||
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, uint32_t port_id, int speed);
|
||||
void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue