mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
qca: ipq40xx: Enable spi nor driver in fifo mode
Change-Id: I641f2a206f0537c6b715841447100dcbe89f87b3 Signed-off-by: Akila N <akilan@codeaurora.org>
This commit is contained in:
Akila N
parent
27d0f93300
commit
1aa59e6721
6 changed files with 1000 additions and 3 deletions
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@ -24,6 +24,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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loff_t board_env_offset;
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loff_t board_env_range;
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loff_t board_env_size;
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/*
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* Don't have this as a '.bss' variable. The '.bss' and '.rel.dyn'
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* sections seem to overlap.
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@ -68,7 +72,7 @@ static board_ipq40xx_params_t *get_board_param(unsigned int machid)
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{
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unsigned int index;
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printf("machid : 0x%0x\n", machid);
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printf("machid: %x\n", machid);
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for (index = 0; index < NUM_IPQ40XX_BOARDS; index++) {
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if (machid == board_params[index].machid)
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return &board_params[index];
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@ -78,13 +82,112 @@ static board_ipq40xx_params_t *get_board_param(unsigned int machid)
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for (;;);
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}
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int board_init(void)
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{
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int ret;
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uint32_t start_blocks;
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uint32_t size_blocks;
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qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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gd->bd->bi_boot_params = QCA_BOOT_PARAMS_ADDR;
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gd->bd->bi_arch_number = smem_get_board_platform_type();
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gboard_param = get_board_param(gd->bd->bi_arch_number);
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ret = smem_get_boot_flash(&sfi->flash_type,
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&sfi->flash_index,
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&sfi->flash_chip_select,
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&sfi->flash_block_size,
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&sfi->flash_density);
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if (ret < 0) {
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printf("cdp: get boot flash failed\n");
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return ret;
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}
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/*
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* Should be inited, before env_relocate() is called,
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* since env. offset is obtained from SMEM.
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*/
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if (sfi->flash_type != SMEM_BOOT_MMC_FLASH) {
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ret = smem_ptable_init();
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if (ret < 0) {
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printf("cdp: SMEM init failed\n");
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return ret;
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}
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}
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if (sfi->flash_type != SMEM_BOOT_MMC_FLASH) {
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ret = smem_getpart("0:APPSBLENV", &start_blocks, &size_blocks);
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if (ret < 0) {
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printf("cdp: get environment part failed\n");
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return ret;
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}
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board_env_offset = ((loff_t) sfi->flash_block_size) * start_blocks;
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board_env_size = ((loff_t) sfi->flash_block_size) * size_blocks;
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}
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if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) {
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board_env_range = CONFIG_ENV_SIZE_MAX;
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BUG_ON(board_env_size < CONFIG_ENV_SIZE_MAX);
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} else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
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board_env_range = board_env_size;
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BUG_ON(board_env_size > CONFIG_ENV_SIZE_MAX);
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#ifdef CONFIG_QCA_MMC
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} else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) {
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board_env_range = CONFIG_ENV_SIZE_MAX;
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#endif
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} else {
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printf("BUG: unsupported flash type : %d\n", sfi->flash_type);
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BUG();
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}
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return 0;
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}
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void qca_get_part_details(void)
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{
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int ret, i;
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uint32_t start; /* block number */
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uint32_t size; /* no. of blocks */
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qca_smem_flash_info_t *smem = &qca_smem_flash_info;
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struct { char *name; qca_part_entry_t *part; } entries[] = {
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{ "0:HLOS", &smem->hlos },
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{ "rootfs", &smem->rootfs },
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};
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for (i = 0; i < ARRAY_SIZE(entries); i++) {
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ret = smem_getpart(entries[i].name, &start, &size);
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if (ret < 0) {
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qca_part_entry_t *part = entries[i].part;
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debug("cdp: get part failed for %s\n", entries[i].name);
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part->offset = 0xBAD0FF5E;
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part->size = 0xBAD0FF5E;
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} else {
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qca_set_part_entry(entries[i].name, smem, entries[i].part, start, size);
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}
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}
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return;
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}
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int board_late_init(void)
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{
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unsigned int machid;
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qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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if (sfi->flash_type != SMEM_BOOT_MMC_FLASH) {
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qca_get_part_details();
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}
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/* get machine type from SMEM and set in env */
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machid = gd->bd->bi_arch_number;
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printf("machid: %x\n", machid);
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if (machid != 0) {
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setenv_addr("machid", (void *)machid);
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gd->bd->bi_arch_number = machid;
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}
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return 0;
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}
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@ -32,6 +32,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
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{"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
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#endif
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#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
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{"GD25Q16", 0xc84015, 0x0, 64 * 1024, 32, RD_NORM, 0},
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{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
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#endif
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@ -48,9 +49,13 @@ const struct spi_flash_params spi_flash_params_table[] = {
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{"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
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{"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"MX25L25635E", 0xc22019, 0x0, 64 * 1024, 512, RD_NORM, 0},
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{"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
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{"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
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{"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
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{"MX25U3235F", 0xc2536, 0x0, 64 * 1024, 64, RD_NORM, 0},
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{"MX25U6435F", 0xc22537, 0x0, 64 * 1024, 128, RD_NORM, 0},
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{"MX25U25635F", 0xc22539, 0x0, 64 * 1024, 512, RD_NORM, 0},
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#endif
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#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
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{"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
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@ -32,6 +32,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
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obj-$(CONFIG_ICH_SPI) += ich.o
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obj-$(CONFIG_QCA_SPI) += qca_qup_spi.o
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obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
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obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
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654
drivers/spi/qca_qup_spi.c
Normal file
654
drivers/spi/qca_qup_spi.c
Normal file
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@ -0,0 +1,654 @@
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/*
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* BLSP QUP SPI controller driver.
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <dm.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch-qcom-common/gpio.h>
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#include <asm/arch-ipq40xx/iomap.h>
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#include "qca_qup_spi.h"
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static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay)
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{
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unsigned int count = TIMEOUT_CNT;
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unsigned int bit_val = ((readl(reg_addr) >> bit_num) & 0x01);
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while (bit_val != val) {
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count--;
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if (count == 0)
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return -ETIMEDOUT;
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udelay(us_delay);
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bit_val = ((readl(reg_addr) >> bit_num) & 0x01);
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}
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return SUCCESS;
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}
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/*
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* Check whether QUPn State is valid
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*/
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static int check_qup_state_valid(struct ipq_spi_slave *ds)
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{
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return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_BIT,
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QUP_STATE_VALID, 1);
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}
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/*
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* Configure QUPn Core state
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*/
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static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state)
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{
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uint32_t val;
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int ret = SUCCESS;
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ret = check_qup_state_valid(ds);
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if (ret != SUCCESS)
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return ret;
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switch (state) {
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case SPI_RUN_STATE:
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/* Set the state to RUN */
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val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK)
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| QUP_STATE_RUN_STATE);
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writel(val, ds->regs->qup_state);
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ret = check_qup_state_valid(ds);
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if (ret != SUCCESS)
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return ret;
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ds->core_state = SPI_CORE_RUNNING;
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break;
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case SPI_RESET_STATE:
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/* Set the state to RESET */
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val = ((readl(ds->regs->qup_state) & ~QUP_STATE_MASK)
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| QUP_STATE_RESET_STATE);
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writel(val, ds->regs->qup_state);
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ret = check_qup_state_valid(ds);
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if (ret != SUCCESS)
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return ret;
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ds->core_state = SPI_CORE_RESET;
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break;
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default:
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printf("err: unsupported QUP SPI state : %d\n", state);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/*
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* Set QUPn SPI Mode
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*/
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static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode)
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{
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unsigned int clk_idle_state;
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unsigned int input_first_mode;
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uint32_t val;
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switch (mode) {
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case SPI_MODE0:
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clk_idle_state = 0;
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input_first_mode = SPI_INPUT_FIRST_MODE;
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break;
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case SPI_MODE1:
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clk_idle_state = 0;
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input_first_mode = 0;
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break;
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case SPI_MODE2:
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clk_idle_state = 1;
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input_first_mode = SPI_INPUT_FIRST_MODE;
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break;
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case SPI_MODE3:
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clk_idle_state = 1;
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input_first_mode = 0;
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break;
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default:
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printf("err : unsupported spi mode : %d\n", mode);
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return;
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}
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val = readl(ds->regs->spi_config);
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val |= input_first_mode;
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writel(val, ds->regs->spi_config);
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val = readl(ds->regs->io_control);
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if (clk_idle_state)
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val |= SPI_IO_CONTROL_CLOCK_IDLE_HIGH;
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else
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val &= ~SPI_IO_CONTROL_CLOCK_IDLE_HIGH;
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writel(val, ds->regs->io_control);
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}
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/*
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* Reset entire QUP and all mini cores
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*/
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static void spi_reset(struct ipq_spi_slave *ds)
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{
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writel(0x1, ds->regs->qup_sw_reset);
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udelay(5);
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}
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ipq_spi_slave *ds;
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ds = malloc(sizeof(struct ipq_spi_slave));
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if (!ds) {
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printf("SPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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/*
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* QCA BLSP supports SPI Flash
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* on different BLSP0 and BLSP1
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* with different number of chip selects (CS, channels):
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*/
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if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI)
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|| ((bus == BLSP0_SPI) && (cs > 2))
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|| ((bus == BLSP1_SPI) && (cs > 0))) {
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printf("SPI error: unsupported bus %d "
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"(Supported busses 0,1 and 2) or chipselect\n", bus);
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goto err;
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}
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ds->slave.bus = bus;
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ds->slave.cs = cs;
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ds->slave.memory_map = NULL;
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ds->slave.option = 0;
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ds->regs = &spi_reg[bus];
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/* TODO For different clock frequency */
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if (max_hz > MSM_QUP_MAX_FREQ) {
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printf("SPI error: unsupported frequency %d Hz "
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"Max frequency is %d Hz\n", max_hz, MSM_QUP_MAX_FREQ);
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goto err;
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}
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ds->freq = max_hz;
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if (mode > SPI_MODE3) {
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printf("SPI error: unsupported SPI mode %d\n", mode);
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goto err;
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}
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ds->mode = mode;
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return &ds->slave;
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err:
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free(ds);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ipq_spi_slave *ds = to_ipq_spi(slave);
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if (ds != NULL)
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free(ds);
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}
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/*
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* BLSP QUPn SPI Hardware Initialisation
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*/
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static int spi_hw_init(struct ipq_spi_slave *ds)
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{
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int ret;
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ds->initialized = 0;
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/* QUPn module configuration */
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spi_reset(ds);
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/* Set the QUPn state */
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ret = config_spi_state(ds, SPI_RESET_STATE);
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if (ret)
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return ret;
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/*
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* Configure Mini core to SPI core with Input Output enabled,
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* SPI master, N = 8 bits
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*/
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clrsetbits_le32(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK |
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QUP_CONF_INPUT_MSK |
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QUP_CONF_OUTPUT_MSK |
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SPI_BIT_WORD_MSK),
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(QUP_CONFIG_MINI_CORE_SPI |
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QUP_CONF_INPUT_ENA |
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QUP_CONF_OUTPUT_ENA |
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SPI_8_BIT_WORD));
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/*
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* Configure Input first SPI protocol,
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* SPI master mode and no loopback
|
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*/
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clrsetbits_le32(ds->regs->spi_config, (LOOP_BACK_MSK |
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SLAVE_OPERATION_MSK),
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(NO_LOOP_BACK |
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SLAVE_OPERATION));
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/*
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* Configure SPI IO Control Register
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* CLK_ALWAYS_ON = 0
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* MX_CS_MODE = 0
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* NO_TRI_STATE = 1
|
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*/
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writel((CLK_ALWAYS_ON | NO_TRI_STATE),
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ds->regs->io_control);
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/*
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* Configure SPI IO Modes.
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* OUTPUT_BIT_SHIFT_EN = 1
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* INPUT_MODE = Block Mode
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* OUTPUT MODE = Block Mode
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*/
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clrsetbits_le32(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK |
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INPUT_BLOCK_MODE_MSK |
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OUTPUT_BLOCK_MODE_MSK),
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(OUTPUT_BIT_SHIFT_EN |
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INPUT_BLOCK_MODE |
|
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OUTPUT_BLOCK_MODE));
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spi_set_mode(ds, ds->mode);
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/* Disable Error mask */
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writel(0, ds->regs->error_flags_en);
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writel(0, ds->regs->qup_error_flags_en);
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writel(0, ds->regs->qup_deassert_wait);
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ds->initialized = 1;
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return SUCCESS;
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}
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||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
struct ipq_spi_slave *ds = to_ipq_spi(slave);
|
||||
unsigned int ret;
|
||||
|
||||
ret = spi_hw_init(ds);
|
||||
if (ret)
|
||||
return -EIO;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
struct ipq_spi_slave *ds = to_ipq_spi(slave);
|
||||
|
||||
/* Reset the SPI hardware */
|
||||
spi_reset(ds);
|
||||
ds->initialized = 0;
|
||||
}
|
||||
|
||||
static void write_force_cs(struct spi_slave *slave, int assert)
|
||||
{
|
||||
struct ipq_spi_slave *ds = to_ipq_spi(slave);
|
||||
|
||||
if (assert)
|
||||
clrsetbits_le32(ds->regs->io_control,
|
||||
FORCE_CS_MSK, FORCE_CS_EN);
|
||||
else
|
||||
clrsetbits_le32(ds->regs->io_control,
|
||||
FORCE_CS_MSK, FORCE_CS_DIS);
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to write data to OUTPUT FIFO
|
||||
*/
|
||||
static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data)
|
||||
{
|
||||
/* Wait for space in the FIFO */
|
||||
while ((readl(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL))
|
||||
udelay(1);
|
||||
|
||||
/* Write the byte of data */
|
||||
writel(data, ds->regs->qup_output_fifo);
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to read data from Input FIFO
|
||||
*/
|
||||
static unsigned char spi_read_byte(struct ipq_spi_slave *ds)
|
||||
{
|
||||
/* Wait for Data in FIFO */
|
||||
while (!(readl(ds->regs->qup_operational) &
|
||||
QUP_DATA_AVAILABLE_FOR_READ)) {
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Read a byte of data */
|
||||
return readl(ds->regs->qup_input_fifo) & 0xff;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to check wheather Input or Output FIFO
|
||||
* has data to be serviced
|
||||
*/
|
||||
static int check_fifo_status(uint32_t reg_addr)
|
||||
{
|
||||
unsigned int count = TIMEOUT_CNT;
|
||||
unsigned int status_flag;
|
||||
unsigned int val;
|
||||
|
||||
do {
|
||||
val = readl(reg_addr);
|
||||
count--;
|
||||
if (count == 0)
|
||||
return -ETIMEDOUT;
|
||||
status_flag = ((val & OUTPUT_SERVICE_FLAG) | (val & INPUT_SERVICE_FLAG));
|
||||
} while (!status_flag);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to configure Input and Output enable/disable
|
||||
*/
|
||||
static void enable_io_config(struct ipq_spi_slave *ds,
|
||||
uint32_t write_cnt, uint32_t read_cnt)
|
||||
{
|
||||
|
||||
if (write_cnt) {
|
||||
clrsetbits_le32(ds->regs->qup_config,
|
||||
QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
|
||||
} else {
|
||||
clrsetbits_le32(ds->regs->qup_config,
|
||||
QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
|
||||
}
|
||||
|
||||
if (read_cnt) {
|
||||
clrsetbits_le32(ds->regs->qup_config,
|
||||
QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
|
||||
} else {
|
||||
clrsetbits_le32(ds->regs->qup_config,
|
||||
QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to read bytes number of data from the Input FIFO
|
||||
*/
|
||||
static int __blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer,
|
||||
unsigned int bytes)
|
||||
{
|
||||
uint32_t val;
|
||||
unsigned int i;
|
||||
unsigned int read_bytes = bytes;
|
||||
unsigned int fifo_count;
|
||||
int ret = SUCCESS;
|
||||
int state_config;
|
||||
|
||||
/* Configure no of bytes to read */
|
||||
state_config = config_spi_state(ds, SPI_RESET_STATE);
|
||||
if (state_config)
|
||||
return state_config;
|
||||
|
||||
/* Configure input and output enable */
|
||||
enable_io_config(ds, 0, read_bytes);
|
||||
|
||||
writel(bytes, ds->regs->qup_mx_input_count);
|
||||
|
||||
state_config = config_spi_state(ds, SPI_RUN_STATE);
|
||||
if (state_config)
|
||||
return state_config;
|
||||
|
||||
while (read_bytes) {
|
||||
ret = check_fifo_status(ds->regs->qup_operational);
|
||||
if (ret != SUCCESS)
|
||||
goto out;
|
||||
|
||||
val = readl(ds->regs->qup_operational);
|
||||
if (val & INPUT_SERVICE_FLAG) {
|
||||
/*
|
||||
* acknowledge to hw that software will
|
||||
* read input data
|
||||
*/
|
||||
val &= INPUT_SERVICE_FLAG;
|
||||
writel(val, ds->regs->qup_operational);
|
||||
|
||||
fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
|
||||
SPI_INPUT_BLOCK_SIZE : read_bytes);
|
||||
|
||||
for (i = 0; i < fifo_count; i++) {
|
||||
*data_buffer = spi_read_byte(ds);
|
||||
data_buffer++;
|
||||
read_bytes--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
/*
|
||||
* Put the SPI Core back in the Reset State
|
||||
* to end the transfer
|
||||
*/
|
||||
(void)config_spi_state(ds, SPI_RESET_STATE);
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
static int blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer,
|
||||
unsigned int bytes)
|
||||
{
|
||||
int length, ret;
|
||||
|
||||
while (bytes) {
|
||||
length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
|
||||
|
||||
ret = __blsp_spi_read(ds, data_buffer, length);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
data_buffer += length;
|
||||
bytes -= length;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to write data to the Output FIFO
|
||||
*/
|
||||
static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer,
|
||||
unsigned int bytes)
|
||||
{
|
||||
uint32_t val;
|
||||
unsigned int i;
|
||||
unsigned int write_len = bytes;
|
||||
unsigned int read_len = bytes;
|
||||
unsigned int fifo_count;
|
||||
int ret = SUCCESS;
|
||||
int state_config;
|
||||
|
||||
state_config = config_spi_state(ds, SPI_RESET_STATE);
|
||||
if (state_config)
|
||||
return state_config;
|
||||
|
||||
/* No of bytes to be written in Output FIFO */
|
||||
writel(bytes, ds->regs->qup_mx_output_count);
|
||||
writel(bytes, ds->regs->qup_mx_input_count);
|
||||
state_config = config_spi_state(ds, SPI_RUN_STATE);
|
||||
if (state_config)
|
||||
return state_config;
|
||||
|
||||
/* Configure input and output enable */
|
||||
enable_io_config(ds, write_len, read_len);
|
||||
|
||||
/*
|
||||
* read_len considered to ensure that we read the dummy data for the
|
||||
* write we performed. This is needed to ensure with WR-RD transaction
|
||||
* to get the actual data on the subsequent read cycle that happens
|
||||
*/
|
||||
while (write_len || read_len) {
|
||||
|
||||
ret = check_fifo_status(ds->regs->qup_operational);
|
||||
if (ret != SUCCESS)
|
||||
goto out;
|
||||
|
||||
val = readl(ds->regs->qup_operational);
|
||||
if (val & OUTPUT_SERVICE_FLAG) {
|
||||
/*
|
||||
* acknowledge to hw that software will write
|
||||
* expected output data
|
||||
*/
|
||||
val &= OUTPUT_SERVICE_FLAG;
|
||||
writel(val, ds->regs->qup_operational);
|
||||
|
||||
if (write_len > SPI_OUTPUT_BLOCK_SIZE)
|
||||
fifo_count = SPI_OUTPUT_BLOCK_SIZE;
|
||||
else
|
||||
fifo_count = write_len;
|
||||
|
||||
for (i = 0; i < fifo_count; i++) {
|
||||
/* Write actual data to output FIFO */
|
||||
spi_write_byte(ds, *cmd_buffer);
|
||||
cmd_buffer++;
|
||||
write_len--;
|
||||
}
|
||||
}
|
||||
if (val & INPUT_SERVICE_FLAG) {
|
||||
/*
|
||||
* acknowledge to hw that software
|
||||
* will read input data
|
||||
*/
|
||||
val &= INPUT_SERVICE_FLAG;
|
||||
writel(val, ds->regs->qup_operational);
|
||||
|
||||
if (read_len > SPI_INPUT_BLOCK_SIZE)
|
||||
fifo_count = SPI_INPUT_BLOCK_SIZE;
|
||||
else
|
||||
fifo_count = read_len;
|
||||
|
||||
for (i = 0; i < fifo_count; i++) {
|
||||
/* Read dummy data for the data written */
|
||||
(void)spi_read_byte(ds);
|
||||
|
||||
/* Decrement the write count after reading the dummy data
|
||||
* from the device. This is to make sure we read dummy data
|
||||
* before we write the data to fifo
|
||||
*/
|
||||
read_len--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
/*
|
||||
* Put the SPI Core back in the Reset State
|
||||
* to end the transfer
|
||||
*/
|
||||
(void)config_spi_state(ds, SPI_RESET_STATE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int blsp_spi_write(struct ipq_spi_slave *ds, u8 *cmd_buffer,
|
||||
unsigned int bytes)
|
||||
{
|
||||
int length, ret;
|
||||
|
||||
while (bytes) {
|
||||
length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
|
||||
|
||||
ret = __blsp_spi_write(ds, cmd_buffer, length);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
cmd_buffer += length;
|
||||
bytes -= length;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*
|
||||
* This function is invoked with either tx_buf or rx_buf.
|
||||
* Calling this function with both null does a chip select change.
|
||||
*/
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct ipq_spi_slave *ds = to_ipq_spi(slave);
|
||||
unsigned int len;
|
||||
const u8 *txp = dout;
|
||||
u8 *rxp = din;
|
||||
int ret;
|
||||
|
||||
if (bitlen & 0x07) {
|
||||
printf("err : Invalid bit length");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
len = bitlen >> 3;
|
||||
|
||||
if (flags & SPI_XFER_BEGIN) {
|
||||
ret = spi_hw_init(ds);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
write_force_cs(slave, 1);
|
||||
}
|
||||
|
||||
if (dout != NULL) {
|
||||
ret = blsp_spi_write(ds, txp, len);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (din != NULL) {
|
||||
ret = blsp_spi_read(ds, rxp, len);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (flags & SPI_XFER_END) {
|
||||
/* To handle only when chip select change is needed */
|
||||
write_force_cs(slave, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
|
||||
}
|
||||
217
drivers/spi/qca_qup_spi.h
Normal file
217
drivers/spi/qca_qup_spi.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Register definitions for the IPQ40XX QUP-SPI Controller
|
||||
* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _IPQ40XX_SPI_H_
|
||||
#define _IPQ40XX_SPI_H_
|
||||
|
||||
#define QUP0_BASE 0x78b5000
|
||||
#define QUP1_BASE 0x78b6000
|
||||
|
||||
#define BLSP0_QUP_REG_BASE (QUP0_BASE + 0x00000000)
|
||||
#define BLSP1_QUP_REG_BASE (QUP1_BASE + 0x00000000)
|
||||
|
||||
#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
|
||||
#define BLSP1_SPI_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000300)
|
||||
|
||||
#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
|
||||
#define BLSP1_SPI_IO_CONTROL_REG (BLSP1_QUP_REG_BASE + 0x00000304)
|
||||
|
||||
#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
|
||||
#define BLSP1_SPI_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x00000308)
|
||||
|
||||
#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
|
||||
#define BLSP1_SPI_DEASSERT_WAIT_REG (BLSP1_QUP_REG_BASE + 0x00000310)
|
||||
#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
|
||||
#define BLSP1_SPI_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x0000030c)
|
||||
|
||||
#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
|
||||
#define BLSP1_QUP_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000000)
|
||||
|
||||
#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
|
||||
#define BLSP1_QUP_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x0000001c)
|
||||
|
||||
#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
|
||||
#define BLSP1_QUP_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x00000020)
|
||||
|
||||
#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
|
||||
#define BLSP1_QUP_OPERATIONAL_MASK (BLSP1_QUP_REG_BASE + 0x00000028)
|
||||
|
||||
#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
|
||||
#define BLSP1_QUP_OPERATIONAL_REG (BLSP1_QUP_REG_BASE + 0x00000018)
|
||||
|
||||
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
|
||||
#define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
|
||||
|
||||
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
|
||||
#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
|
||||
|
||||
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
|
||||
(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
|
||||
#define BLSP1_QUP_INPUT_FIFOc_REG(c) \
|
||||
(BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
|
||||
|
||||
#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
|
||||
(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
|
||||
#define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
|
||||
(BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
|
||||
|
||||
#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
|
||||
#define BLSP1_QUP_MX_INPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000200)
|
||||
|
||||
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
|
||||
#define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
|
||||
|
||||
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
|
||||
#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
|
||||
|
||||
#define QUP_STATE_VALID_BIT 2
|
||||
#define QUP_STATE_VALID 1
|
||||
#define QUP_STATE_MASK 0x3
|
||||
#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
|
||||
#define QUP_CONFIG_MINI_CORE_SPI (1 << 8)
|
||||
#define QUP_CONF_INPUT_MSK (1 << 7)
|
||||
#define QUP_CONF_INPUT_ENA (0 << 7)
|
||||
#define QUP_CONF_NO_INPUT (1 << 7)
|
||||
#define QUP_CONF_OUTPUT_MSK (1 << 6)
|
||||
#define QUP_CONF_OUTPUT_ENA (0 << 6)
|
||||
#define QUP_CONF_NO_OUTPUT (1 << 6)
|
||||
#define QUP_STATE_RUN_STATE 0x1
|
||||
#define QUP_STATE_RESET_STATE 0x0
|
||||
#define QUP_STATE_PAUSE_STATE 0x3
|
||||
#define SPI_BIT_WORD_MSK 0x1F
|
||||
#define SPI_8_BIT_WORD 0x07
|
||||
#define LOOP_BACK_MSK (1 << 8)
|
||||
#define NO_LOOP_BACK (0 << 8)
|
||||
#define SLAVE_OPERATION_MSK (1 << 5)
|
||||
#define SLAVE_OPERATION (0 << 5)
|
||||
#define CLK_ALWAYS_ON (0 << 9)
|
||||
#define MX_CS_MODE (1 << 8)
|
||||
#define NO_TRI_STATE (1 << 0)
|
||||
#define FORCE_CS_MSK (1 << 11)
|
||||
#define FORCE_CS_EN (1 << 11)
|
||||
#define FORCE_CS_DIS (0 << 11)
|
||||
#define OUTPUT_BIT_SHIFT_MSK (1 << 16)
|
||||
#define OUTPUT_BIT_SHIFT_EN (1 << 16)
|
||||
#define INPUT_BLOCK_MODE_MSK (0x03 << 12)
|
||||
#define INPUT_BLOCK_MODE (0x01 << 12)
|
||||
#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
|
||||
#define OUTPUT_BLOCK_MODE (0x01 << 10)
|
||||
|
||||
#define SPI_INPUT_FIRST_MODE (1 << 9)
|
||||
#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10)
|
||||
#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5)
|
||||
#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4)
|
||||
#define OUTPUT_SERVICE_FLAG (1 << 8)
|
||||
#define INPUT_SERVICE_FLAG (1 << 9)
|
||||
#define QUP_OUTPUT_FIFO_FULL (1 << 6)
|
||||
#define SPI_INPUT_BLOCK_SIZE 4
|
||||
#define SPI_OUTPUT_BLOCK_SIZE 4
|
||||
#define MSM_QUP_MAX_FREQ 51200000
|
||||
#define MAX_COUNT_SIZE 0xffff
|
||||
|
||||
#define SPI_RESET_STATE 0
|
||||
#define SPI_RUN_STATE 1
|
||||
#define SPI_CORE_RESET 0
|
||||
#define SPI_CORE_RUNNING 1
|
||||
#define SPI_MODE0 0
|
||||
#define SPI_MODE1 1
|
||||
#define SPI_MODE2 2
|
||||
#define SPI_MODE3 3
|
||||
#define BLSP0_SPI 0
|
||||
#define BLSP1_SPI 1
|
||||
|
||||
struct blsp_spi {
|
||||
unsigned int spi_config;
|
||||
unsigned int io_control;
|
||||
unsigned int error_flags;
|
||||
unsigned int error_flags_en;
|
||||
unsigned int qup_config;
|
||||
unsigned int qup_error_flags;
|
||||
unsigned int qup_error_flags_en;
|
||||
unsigned int qup_operational;
|
||||
unsigned int qup_io_modes;
|
||||
unsigned int qup_state;
|
||||
unsigned int qup_input_fifo;
|
||||
unsigned int qup_output_fifo;
|
||||
unsigned int qup_mx_input_count;
|
||||
unsigned int qup_mx_output_count;
|
||||
unsigned int qup_sw_reset;
|
||||
unsigned int qup_ns_reg;
|
||||
unsigned int qup_md_reg;
|
||||
unsigned int qup_op_mask;
|
||||
unsigned int qup_deassert_wait;
|
||||
};
|
||||
|
||||
static const struct blsp_spi spi_reg[] = {
|
||||
/* BLSP0 registers for SPI interface */
|
||||
{
|
||||
BLSP0_SPI_CONFIG_REG,
|
||||
BLSP0_SPI_IO_CONTROL_REG,
|
||||
BLSP0_SPI_ERROR_FLAGS_REG,
|
||||
BLSP0_SPI_ERROR_FLAGS_EN_REG,
|
||||
BLSP0_QUP_CONFIG_REG,
|
||||
BLSP0_QUP_ERROR_FLAGS_REG,
|
||||
BLSP0_QUP_ERROR_FLAGS_EN_REG,
|
||||
BLSP0_QUP_OPERATIONAL_REG,
|
||||
BLSP0_QUP_IO_MODES_REG,
|
||||
BLSP0_QUP_STATE_REG,
|
||||
BLSP0_QUP_INPUT_FIFOc_REG(0),
|
||||
BLSP0_QUP_OUTPUT_FIFOc_REG(0),
|
||||
BLSP0_QUP_MX_INPUT_COUNT_REG,
|
||||
BLSP0_QUP_MX_OUTPUT_COUNT_REG,
|
||||
BLSP0_QUP_SW_RESET_REG,
|
||||
BLSP0_QUP_OPERATIONAL_MASK,
|
||||
BLSP0_SPI_DEASSERT_WAIT_REG,
|
||||
},
|
||||
/* BLSP1 registers for SPI interface */
|
||||
{
|
||||
BLSP1_SPI_CONFIG_REG,
|
||||
BLSP1_SPI_IO_CONTROL_REG,
|
||||
BLSP1_SPI_ERROR_FLAGS_REG,
|
||||
BLSP1_SPI_ERROR_FLAGS_EN_REG,
|
||||
BLSP1_QUP_CONFIG_REG,
|
||||
BLSP1_QUP_ERROR_FLAGS_REG,
|
||||
BLSP1_QUP_ERROR_FLAGS_EN_REG,
|
||||
BLSP1_QUP_OPERATIONAL_REG,
|
||||
BLSP1_QUP_IO_MODES_REG,
|
||||
BLSP1_QUP_STATE_REG,
|
||||
BLSP1_QUP_INPUT_FIFOc_REG(0),
|
||||
BLSP1_QUP_OUTPUT_FIFOc_REG(0),
|
||||
BLSP1_QUP_MX_INPUT_COUNT_REG,
|
||||
BLSP1_QUP_MX_OUTPUT_COUNT_REG,
|
||||
BLSP1_QUP_SW_RESET_REG,
|
||||
BLSP1_QUP_OPERATIONAL_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
#define SUCCESS 0
|
||||
|
||||
#define DUMMY_DATA_VAL 0
|
||||
#define TIMEOUT_CNT 100
|
||||
|
||||
struct ipq_spi_slave {
|
||||
struct spi_slave slave;
|
||||
const struct blsp_spi *regs;
|
||||
unsigned int core_state;
|
||||
unsigned int mode;
|
||||
unsigned int initialized;
|
||||
unsigned long freq;
|
||||
};
|
||||
|
||||
static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
|
||||
{
|
||||
return container_of(slave, struct ipq_spi_slave, slave);
|
||||
}
|
||||
|
||||
#endif /* _IPQ_SPI_H_ */
|
||||
|
|
@ -85,10 +85,10 @@ typedef struct {
|
|||
|
||||
#define CONFIG_QCA_SMEM_BASE 0x87e00000
|
||||
#define QCA_KERNEL_START_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + GENERATED_QCA_RESERVE_SIZE)
|
||||
(CONFIG_SYS_SDRAM_BASE + sizeof(qca_mem_reserve_t))
|
||||
|
||||
#define QCA_DRAM_KERNEL_SIZE \
|
||||
(CONFIG_SYS_SDRAM_SIZE - GENERATED_QCA_RESERVE_SIZE)
|
||||
(CONFIG_SYS_SDRAM_SIZE - sizeof(qca_mem_reserve_t))
|
||||
|
||||
#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
|
||||
#endif
|
||||
|
|
@ -114,6 +114,23 @@ typedef struct {
|
|||
* size is configured to 64 */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
/*
|
||||
* SPI Flash Configs
|
||||
*/
|
||||
|
||||
#define CONFIG_QCA_SPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
#define CONFIG_SPI_FLASH_GIGADEVICE
|
||||
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SPI_FLASH_BAR 1
|
||||
|
||||
#define CONFIG_IPQ40XX_EDMA 1
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue