ipq9048: Enable mmc support

Change-Id: If260475979df0eb5d50cbe232060bc38613847d4
Signed-off-by: anusha <anusharao@codeaurora.org>

arch/arm/dts/ipq9048-emulation.dts

@@ -22,6 +22,7 @@
 	aliases {
 		console = "/serial@78AF000";
 		nand = "/nand-controller@79B0000";
+		mmc = "/sdhci@7804000";
 	};
 
 	timer {
@@ -32,4 +33,8 @@
 		status = "okay";
 		nand_gpio {};
 	};
+
+	mmc: sdhci@7804000 {
+		compatible = "qcom,sdhci-msm";
+	};
 };

arch/arm/dts/ipq9048-soc.dtsi

@@ -62,6 +62,10 @@
 		status = "disabled";
 	};
 
+	mmc: sdhci@7804000 {
+		compatible = "qcom,sdhci-msm";
+	};
+
 	timer {
 		gcnt_cntcv_lo = <0x4a2000>;
 		gcnt_cntcv_hi = <0x4a2004>;

arch/arm/include/asm/arch-ipq9048/clk.h

@@ -52,6 +52,10 @@
 #define NOT_N_MINUS_M(n,m)	(~(n - m))
 #define CLOCK_UPDATE_TIMEOUT_US	1000
 
+#define CMD_UPDATE      0x1
+#define ROOT_EN         0x2
+#define CLK_ENABLE      0x1
+
 int uart_clock_config(struct ipq_serial_platdata *plat);
 
 #endif /*IPQ9048_CLK_H*/

board/qca/arm/ipq9048/ipq9048.c

@@ -22,8 +22,11 @@
 #include <asm/arch-qca-common/gpio.h>
 #include <asm/arch-qca-common/uart.h>
 #include <ipq9048.h>
+#include <mmc.h>
+#include <sdhci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+struct sdhci_host mmc_host;
 extern int ipq_spi_init(u16);
 
 unsigned int qpic_frequency = 0, qpic_phase = 0;
@@ -166,6 +169,110 @@ void board_nand_init(void)
 #endif
 }
 
+#ifdef CONFIG_QCA_MMC
+void emmc_clock_config(void)
+{
+#ifndef CONFIG_IPQ9048_RUMI
+	int cfg;
+
+	/* Configure sdcc1_apps_clk_src */
+	cfg = (GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL
+			| GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV);
+	writel(cfg, GCC_SDCC1_APPS_CFG_RCGR);
+	writel(SDCC1_M_VAL, GCC_SDCC1_APPS_M);
+	writel(SDCC1_N_VAL, GCC_SDCC1_APPS_N);
+	writel(SDCC1_D_VAL, GCC_SDCC1_APPS_D);
+	writel(CMD_UPDATE, GCC_SDCC1_APPS_CMD_RCGR);
+	mdelay(100);
+	writel(ROOT_EN, GCC_SDCC1_APPS_CMD_RCGR);
+
+	/* Configure CBCRs */
+	writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
+	udelay(10);
+	writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
+#endif
+}
+
+void mmc_iopad_config(struct sdhci_host *host)
+{
+	u32 val;
+	val = sdhci_readb(host, SDHCI_VENDOR_IOPAD);
+	/*set bit 15 & 16*/
+	val |= 0x18000;
+	writel(val, host->ioaddr + SDHCI_VENDOR_IOPAD);
+}
+
+void sdhci_bus_pwr_off(struct sdhci_host *host)
+{
+	u32 val;
+
+	val = sdhci_readb(host, SDHCI_HOST_CONTROL);
+	sdhci_writeb(host,(val & (~SDHCI_POWER_ON)), SDHCI_POWER_CONTROL);
+}
+
+void emmc_clock_disable(void)
+{
+#ifndef CONFIG_IPQ9048_RUMI
+	/* Clear divider */
+	writel(0x0, GCC_SDCC1_MISC);
+#endif
+}
+
+void board_mmc_deinit(void)
+{
+	emmc_clock_disable();
+}
+
+void emmc_clock_reset(void)
+{
+#ifndef CONFIG_IPQ9048_RUMI
+	writel(0x1, GCC_SDCC1_BCR);
+	udelay(10);
+	writel(0x0, GCC_SDCC1_BCR);
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int node;
+	int ret = 0;
+	qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
+
+	node = fdt_path_offset(gd->fdt_blob, "mmc");
+	if (node < 0) {
+		printf("sdhci: Node Not found, skipping initialization\n");
+		return -1;
+	}
+
+	mmc_host.ioaddr = (void *)MSM_SDC1_SDHCI_BASE;
+	mmc_host.voltages = MMC_VDD_165_195;
+	mmc_host.version = SDHCI_SPEC_300;
+	mmc_host.cfg.part_type = PART_TYPE_EFI;
+	mmc_host.quirks = SDHCI_QUIRK_BROKEN_VOLTAGE;
+
+	emmc_clock_disable();
+	emmc_clock_reset();
+	udelay(10);
+	emmc_clock_config();
+
+	if (add_sdhci(&mmc_host, 200000000, 400000)) {
+		printf("add_sdhci fail!\n");
+		return -1;
+	}
+
+	if (!ret && sfi->flash_type == SMEM_BOOT_MMC_FLASH) {
+		ret = board_mmc_env_init(mmc_host);
+	}
+
+	return ret;
+}
+#else
+int board_mmc_init(bd_t *bis)
+{
+	return 0;
+}
+#endif
+
 void enable_caches(void)
 {
 	icache_enable();

board/qca/arm/ipq9048/ipq9048.h

@@ -62,6 +62,25 @@
 #define FB_CLK_BIT			(1 << 4)
 #define UPDATE_EN			0x1
 
+/*
+ * GCC-SDCC Registers
+ */
+#define GCC_SDCC1_APPS_CBCR	0x183302C
+#define GCC_SDCC1_APPS_CFG_RCGR	0x1833008
+#define GCC_SDCC1_APPS_CMD_RCGR	0x1833004
+#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL	(2 << 8)
+#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV	(0xB << 0)
+#define GCC_SDCC1_APPS_M	0x183300C
+#define GCC_SDCC1_APPS_N	0x1833010
+#define GCC_SDCC1_APPS_D	0x1833014
+#define SDCC1_M_VAL		0x1
+#define SDCC1_N_VAL		0xFC
+#define SDCC1_D_VAL		0xFD
+
+#define GCC_SDCC1_BCR		0x1833000
+#define GCC_SDCC1_AHB_CBCR	0x1833034
+
+
 unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
 					 unsigned int, unsigned int);
 
@@ -168,6 +187,9 @@ typedef enum {
 	SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
 } smem_mem_type_t;
 
+#define MSM_SDC1_BASE           0x7800000
+#define MSM_SDC1_SDHCI_BASE     0x7804000
+
 __weak void qgic_init(void) {}
 __weak void handle_noc_err(void) {}
 extern const char *rsvd_node;

configs/ipq9048_defconfig

@@ -100,6 +100,8 @@ CONFIG_CMD_NFS=y
 #
 # CONFIG_CMD_TIME is not set
 CONFIG_CMD_MISC=y
+CONFIG_CMD_PART=y
+CONFIG_PARTITION_UUIDS=y
 # CONFIG_CMD_TIMER is not set
 
 #

include/configs/ipq9048.h

@@ -254,6 +254,23 @@ extern loff_t board_env_size;
  * By default we are disabling it */
 /*#define CONFIG_IPQ_REPORT_L2ERR*/
 
+/*
+ * MMC configs
+ */
+#define CONFIG_QCA_MMC
+
+#ifdef CONFIG_QCA_MMC
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_SDHCI_QCA
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_SDHCI_SUPPORT
+#define CONFIG_MMC_ADMA
+#endif
+
 /*
  * Other commands
  */