From 91b2d3dea4ec2da7d01542f7b4f23d1fb0f65dff Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Wed, 9 Feb 2022 09:36:08 +0530 Subject: [PATCH] ipq9574: clock: Fix clock configuration This patch updates the following: 1) Initializes I2C QUP clocks in U-Boot itself as required without depending on SBL. 2) Removes all CONFIG_IPQ9574_RUMI references. Change-Id: I1fb02861a70bd2b024122fff7810c3373cc2e1cd Signed-off-by: Selvam Sathappan Periakaruppan --- arch/arm/include/asm/arch-ipq9574/clk.h | 19 ++++++- .../include/asm/arch-qca-common/qca_common.h | 2 - board/qca/arm/ipq9574/clock.c | 49 +++++++++---------- board/qca/arm/ipq9574/ipq9574.c | 12 ----- 4 files changed, 41 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/arch-ipq9574/clk.h b/arch/arm/include/asm/arch-ipq9574/clk.h index 19e6e7ea06..9339f01852 100644 --- a/arch/arm/include/asm/arch-ipq9574/clk.h +++ b/arch/arm/include/asm/arch-ipq9574/clk.h @@ -19,12 +19,27 @@ /* I2C clocks configuration */ #ifdef CONFIG_IPQ9574_I2C +#define BLSP1_QUP_BASE 0x078B5000 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x1802018 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x1802024 #define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR 0x180201C #define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL (1 << 8) #define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV (0x1F << 0) +#define GCC_BLSP1_QUP_I2C_OFFSET_INC 0x1000 -#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x1802018 -#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x1802024 +#define GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(id) ((id < 1) ? \ + (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR):\ + (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id))) + +#define GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(id) ((id < 1) ? \ + (GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR):\ + (GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id))) + +#define GCC_BLSP1_QUP_I2C_APPS_CBCR(id) ((id < 1) ? \ + (GCC_BLSP1_QUP1_I2C_APPS_CBCR):\ + (GCC_BLSP1_QUP1_I2C_APPS_CBCR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id))) + +#define I2C_PORT_ID(reg) ((reg - BLSP1_QUP_BASE) / GCC_BLSP1_QUP_I2C_OFFSET_INC) #define CMD_UPDATE 0x1 #define ROOT_EN 0x2 diff --git a/arch/arm/include/asm/arch-qca-common/qca_common.h b/arch/arm/include/asm/arch-qca-common/qca_common.h index d538214fac..f97133e41b 100644 --- a/arch/arm/include/asm/arch-qca-common/qca_common.h +++ b/arch/arm/include/asm/arch-qca-common/qca_common.h @@ -107,10 +107,8 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla int get_eth_mac_address(uchar *enetaddr, uint no_of_macs); void set_ethmac_addr(void); -#ifndef CONFIG_IPQ9574_RUMI void aquantia_phy_reset_init_done(void); void aquantia_phy_reset_init(void); -#endif int bring_sec_core_up(unsigned int cpuid, unsigned int entry, unsigned int arg); int is_secondary_core_off(unsigned int cpuid); diff --git a/board/qca/arm/ipq9574/clock.c b/board/qca/arm/ipq9574/clock.c index 4572671b52..3858d470ed 100644 --- a/board/qca/arm/ipq9574/clock.c +++ b/board/qca/arm/ipq9574/clock.c @@ -12,28 +12,39 @@ */ #include +#include #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_IPQ9574_I2C -void i2c_clock_config(void) +void i2c_clock_config() { -#ifndef CONFIG_IPQ9574_RUMI - int cfg; + int cfg, i2c_id; + int i2c_node; + const u32 *i2c_base; - /* Configure qup1_i2c_apps_clk_src */ - cfg = (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL | - GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV); - writel(cfg, GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR); + i2c_node = fdt_path_offset(gd->fdt_blob, "i2c0"); + if (i2c_node >= 0) { + i2c_base = fdt_getprop(gd->fdt_blob, i2c_node, "reg", NULL); + if (i2c_base) { + i2c_id = I2C_PORT_ID(fdt32_to_cpu(i2c_base[0])); + /* Configure qup1_i2c_apps_clk_src */ + cfg = (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL | + GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV); + writel(cfg, GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(i2c_id)); - writel(CMD_UPDATE, GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR); - mdelay(100); - writel(ROOT_EN, GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR); + writel(CMD_UPDATE, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id)); + mdelay(100); + writel(ROOT_EN, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id)); - /* Configure CBCR */ - writel(CLK_ENABLE, GCC_BLSP1_QUP1_I2C_APPS_CBCR); -#endif + /* Configure CBCR */ + writel(CLK_ENABLE, GCC_BLSP1_QUP_I2C_APPS_CBCR(i2c_id)); + } + } } #endif @@ -159,7 +170,6 @@ void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, int req_clk_src_type #ifdef CONFIG_PCI_IPQ void pcie_v2_clock_init(int pcie_id) { -#ifndef CONFIG_IPQ9574_RUMI int cfg, div; /* Configure pcie_aux_clk_src */ @@ -224,12 +234,10 @@ void pcie_v2_clock_init(int pcie_id) writel(ROOT_EN, GCC_PCIE_REG(GCC_PCIE_RCHNG_CMD_RCGR, pcie_id)); writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AUX_CBCR, pcie_id)); -#endif } void pcie_v2_clock_deinit(int pcie_id) { -#ifndef CONFIG_IPQ9574_RUMI writel(0x0, GCC_PCIE_REG(GCC_PCIE_AUX_CMD_RCGR, 0)); mdelay(100); writel(0x0, GCC_PCIE_REG(GCC_PCIE_AHB_CBCR, pcie_id)); @@ -255,14 +263,12 @@ void pcie_v2_clock_deinit(int pcie_id) writel(0x0, GCC_ANOC_PCIE3_2LANE_M_CBCR); break; } -#endif } #endif #ifdef CONFIG_USB_XHCI_IPQ void usb_clock_init(int id) { -#ifndef CONFIG_IPQ9574_RUMI int cfg; /* Configure usb0_master_clk_src */ cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL | @@ -305,13 +311,11 @@ void usb_clock_init(int id) writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN), GCC_USB0_PHY_CFG_AHB_CBCR); writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR); -#endif } void usb_clock_deinit(void) { -#ifndef CONFIG_IPQ9574_RUMI /* Disable clocks */ writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR); writel(0xcff0, GCC_USB0_MASTER_CBCR); @@ -320,14 +324,12 @@ void usb_clock_deinit(void) writel(0, GCC_USB0_AUX_CBCR); writel(0, GCC_ANOC_USB_AXI_CBCR); writel(0, GCC_SNOC_USB_CBCR); -#endif } #endif #ifdef CONFIG_QCA_MMC void emmc_clock_init(void) { -#ifndef CONFIG_IPQ9574_RUMI int cfg; /* Configure sdcc1_apps_clk_src */ @@ -345,15 +347,12 @@ void emmc_clock_init(void) writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR); udelay(10); writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR); -#endif } void emmc_clock_reset(void) { -#ifndef CONFIG_IPQ9574_RUMI writel(0x1, GCC_SDCC1_BCR); udelay(10); writel(0x0, GCC_SDCC1_BCR); -#endif } #endif diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c index 3448bbd332..24d4262e7f 100644 --- a/board/qca/arm/ipq9574/ipq9574.c +++ b/board/qca/arm/ipq9574/ipq9574.c @@ -108,15 +108,6 @@ void fdt_fixup_qpic(void *blob) } } - -void qpic_emulation_set_clk(void) -{ - writel(QPIC_CBCR_VAL, GCC_QPIC_CBCR_ADDR); - writel(CLK_ENABLE, GCC_QPIC_AHB_CBCR_ADDR); - writel(CLK_ENABLE, GCC_QPIC_SLEEP_CBCR); - writel(CLK_ENABLE, GCC_QPIC_IO_MACRO_CBCR); -} - void board_nand_init(void) { #ifdef CONFIG_QPIC_SERIAL @@ -130,9 +121,6 @@ void board_nand_init(void) if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) { printf("QPIC: disabled, skipping initialization\n"); } else { -#ifdef CONFIG_IPQ9574_RUMI - qpic_emulation_set_clk(); -#endif qpic_nand_init(NULL); } #endif