From aabae370a901ad1fed99ada452e3af63398241c0 Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Mon, 19 Jul 2021 14:15:54 +0530 Subject: [PATCH] ipq9574: Update Ethernet GPIO configurations This patch updates the following: 1) Updates drive strength of all PHY GPIOs to 8MA 2) Updates MDC GPIO_PULL to "NO_PULL" and MDIO GPIO_PULL to "PULL_UP" 3) Removes redundant GPIO_OE bit configuration Change-Id: Ic33ccbb8413b5b99a9718ad67ebbc069982f44db Signed-off-by: Selvam Sathappan Periakaruppan --- board/qca/arm/ipq9574/ipq9574.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c index 48f4b70863..5d7aec2293 100644 --- a/board/qca/arm/ipq9574/ipq9574.c +++ b/board/qca/arm/ipq9574/ipq9574.c @@ -622,8 +622,7 @@ void aquantia_phy_reset_init(void) for (i = 0; i < aquantia_gpio_cnt; i++) { if (aquantia_gpio[i] >= 0) { aquantia_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(aquantia_gpio[i]); - writel(0x203, aquantia_gpio_base); - gpio_direction_output(aquantia_gpio[i], 0x0); + writel(0x2C3, aquantia_gpio_base); } } } @@ -639,8 +638,7 @@ void qca808x_phy_reset_init(void) for (i = 0; i < qca808x_gpio_cnt; i++) { if (qca808x_gpio[i] >= 0) { qca808x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca808x_gpio[i]); - writel(0x203, qca808x_gpio_base); - gpio_direction_output(qca808x_gpio[i], 0x0); + writel(0x2C3, qca808x_gpio_base); } } } @@ -656,8 +654,7 @@ void qca807x_phy_reset_init(void) for (i = 0; i < qca807x_gpio_cnt; i++) { if (qca807x_gpio[i] >=0) { qca807x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca807x_gpio[i]); - writel(0x203, qca807x_gpio_base); - gpio_direction_output(qca807x_gpio[i], 0x0); + writel(0x2C3, qca807x_gpio_base); } } } @@ -721,7 +718,10 @@ void set_function_select_as_mdc_mdio(void) for (i = 0; i < mdc_mdio_gpio_cnt; i++) { if (mdc_mdio_gpio[i] >=0) { mdc_mdio_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(mdc_mdio_gpio[i]); - writel(0xC7, mdc_mdio_gpio_base); + if (i == 0) + writel(0xC4, mdc_mdio_gpio_base); + else + writel(0xC7, mdc_mdio_gpio_base); } } }