From 84932a6b6f05370f2fa059cc7777152965b31674 Mon Sep 17 00:00:00 2001 From: Ram Kumar D Date: Wed, 17 Aug 2022 18:03:50 +0530 Subject: [PATCH 1/2] arm: dts: devsoc: add eth dts configurations for MI01 Added ethernet dts configurations for MI01.1, MI01.1 & MI01.4 Change-Id: I45797b8515ddac3ab8308b811109667f27db4b2a Signed-off-by: Ram Kumar D --- arch/arm/dts/devsoc-01.1.dts | 56 +++++++++++++++++++++++++++++++++++- arch/arm/dts/devsoc-01.2.dts | 56 +++++++++++++++++++++++++++++++++++- arch/arm/dts/devsoc-01.4.dts | 56 +++++++++++++++++++++++++++++++++++- 3 files changed, 165 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/devsoc-01.1.dts b/arch/arm/dts/devsoc-01.1.dts index fc1686ae89..b5a35d1f71 100644 --- a/arch/arm/dts/devsoc-01.1.dts +++ b/arch/arm/dts/devsoc-01.1.dts @@ -148,6 +148,60 @@ ess-switch { switch_mac_mode0 = ; - switch_mac_mode1 = ; + switch_mac_mode1 = ; + aquantia_gpio = <22>; + aquantia_gpio_cnt = <1>; + aquantia_port = <1>; + aquantia_port_cnt = <1>; + qca808x_gpio = <16>; + qca808x_gpio_cnt = <1>; + mdc_mdio_gpio = <27 28>; + + qca8084_switch_enable = <1>; + + port_phyinfo { + port@0 { + phy_address = <0>; + phy_type = ; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + }; + + qca8084_swt_info { + switch_mac_mode0 = ; + switch_mac_mode1 = ; + + port@0 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + port@2 { + phy_address = <2>; + phy_type = ; + }; + port@3 { + phy_address = <3>; + phy_type = ; + }; + port@4 { + phy_address = <0x4>; + phy_type = ; + }; + port@5 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/devsoc-01.2.dts b/arch/arm/dts/devsoc-01.2.dts index 17fd06e750..26d3f90a62 100644 --- a/arch/arm/dts/devsoc-01.2.dts +++ b/arch/arm/dts/devsoc-01.2.dts @@ -160,6 +160,60 @@ ess-switch { switch_mac_mode0 = ; - switch_mac_mode1 = ; + switch_mac_mode1 = ; + aquantia_gpio = <22>; + aquantia_gpio_cnt = <1>; + aquantia_port = <1>; + aquantia_port_cnt = <1>; + qca808x_gpio = <16>; + qca808x_gpio_cnt = <1>; + mdc_mdio_gpio = <27 28>; + + qca8084_switch_enable = <1>; + + port_phyinfo { + port@0 { + phy_address = <0>; + phy_type = ; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + }; + + qca8084_swt_info { + switch_mac_mode0 = ; + switch_mac_mode1 = ; + + port@0 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + port@2 { + phy_address = <2>; + phy_type = ; + }; + port@3 { + phy_address = <3>; + phy_type = ; + }; + port@4 { + phy_address = <0x4>; + phy_type = ; + }; + port@5 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/devsoc-01.4.dts b/arch/arm/dts/devsoc-01.4.dts index e7e06b8341..8ced3f7a72 100644 --- a/arch/arm/dts/devsoc-01.4.dts +++ b/arch/arm/dts/devsoc-01.4.dts @@ -145,6 +145,60 @@ ess-switch { switch_mac_mode0 = ; - switch_mac_mode1 = ; + switch_mac_mode1 = ; + aquantia_gpio = <22>; + aquantia_gpio_cnt = <1>; + aquantia_port = <1>; + aquantia_port_cnt = <1>; + qca808x_gpio = <16>; + qca808x_gpio_cnt = <1>; + mdc_mdio_gpio = <27 28>; + + qca8084_switch_enable = <1>; + + port_phyinfo { + port@0 { + phy_address = <0>; + phy_type = ; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + }; + + qca8084_swt_info { + switch_mac_mode0 = ; + switch_mac_mode1 = ; + + port@0 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + port@1 { + phy_address = <1>; + phy_type = ; + }; + port@2 { + phy_address = <2>; + phy_type = ; + }; + port@3 { + phy_address = <3>; + phy_type = ; + }; + port@4 { + phy_address = <0x4>; + phy_type = ; + }; + port@5 { + phy_address = <0xff>; + phy_type = ; + forced-speed = <2500>; + forced-duplex = <1>; + }; + }; }; }; From e4eb0bb01815445826c9c29a0fcb3d76d9575808 Mon Sep 17 00:00:00 2001 From: Ram Kumar D Date: Thu, 18 Aug 2022 11:18:04 +0530 Subject: [PATCH 2/2] board: qca: devsoc: add reset sequence for AQ & QCA808X Change-Id: I57133628314a7291de9e8b4bdb2ba08c31424571 Signed-off-by: Ram Kumar D --- board/qca/arm/common/board_init.c | 2 +- board/qca/arm/common/cmd_bootqca.c | 2 +- board/qca/arm/devsoc/devsoc.c | 152 +++++++++++++++++++++++++++++ board/qca/arm/devsoc/devsoc.h | 23 ++++- 4 files changed, 175 insertions(+), 4 deletions(-) diff --git a/board/qca/arm/common/board_init.c b/board/qca/arm/common/board_init.c index f10d398971..d3e0a7d51a 100644 --- a/board/qca/arm/common/board_init.c +++ b/board/qca/arm/common/board_init.c @@ -227,7 +227,7 @@ int board_init(void) printf("WARN: ipq_board_usb_init failed\n"); } -#ifdef CONFIG_IPQ9574_EDMA +#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_DEVSOC_EDMA) aquantia_phy_reset_init(); #endif disable_audio_clks(); diff --git a/board/qca/arm/common/cmd_bootqca.c b/board/qca/arm/common/cmd_bootqca.c index 708861ec46..179662a8ec 100644 --- a/board/qca/arm/common/cmd_bootqca.c +++ b/board/qca/arm/common/cmd_bootqca.c @@ -890,7 +890,7 @@ static int do_bootipq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ret = qca_scm_call(SCM_SVC_FUSE, QFPROM_IS_AUTHENTICATE_CMD, &buf, sizeof(char)); -#ifdef CONFIG_IPQ9574_EDMA +#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_DEVSOC_EDMA) aquantia_phy_reset_init_done(); #endif /* diff --git a/board/qca/arm/devsoc/devsoc.c b/board/qca/arm/devsoc/devsoc.c index 292e0c7086..ce556e7b40 100644 --- a/board/qca/arm/devsoc/devsoc.c +++ b/board/qca/arm/devsoc/devsoc.c @@ -39,6 +39,7 @@ #define FLASH_SEL_BIT 7 DECLARE_GLOBAL_DATA_PTR; +static int aq_phy_initialised = 0; extern int devsoc_edma_init(void *cfg); extern int ipq_spi_init(u16); @@ -766,9 +767,160 @@ void set_flash_secondary_type(qca_smem_flash_info_t *smem) }; #ifdef CONFIG_DEVSOC_EDMA +int get_mdc_mdio_gpio(int mdc_mdio_gpio[2]) +{ + int mdc_mdio_gpio_cnt = 2, node; + int res = -1; + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "mdc_mdio_gpio", + (u32 *)mdc_mdio_gpio, mdc_mdio_gpio_cnt); + if (res >= 0) + return mdc_mdio_gpio_cnt; + } + + return res; +} + +void set_function_select_as_mdc_mdio(void) +{ + int mdc_mdio_gpio[2] = {-1, -1}, mdc_mdio_gpio_cnt, i; + unsigned int *mdc_mdio_gpio_base; + uint32_t cfg; + + mdc_mdio_gpio_cnt = get_mdc_mdio_gpio(mdc_mdio_gpio); + if (mdc_mdio_gpio_cnt >= 1) { + for (i = 0; i < mdc_mdio_gpio_cnt; i++) { + if (mdc_mdio_gpio[i] >=0) { + mdc_mdio_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(mdc_mdio_gpio[i]); + if (i == 0) { + cfg = GPIO_DRV_8_MA | MDC_MDIO_FUNC_SEL | GPIO_NO_PULL; + writel(cfg, mdc_mdio_gpio_base); + } else { + cfg = GPIO_DRV_8_MA | MDC_MDIO_FUNC_SEL | GPIO_PULL_UP; + writel(cfg, mdc_mdio_gpio_base); + } + } + } + } +} + +int get_aquantia_gpio(int aquantia_gpio[2]) +{ + int aquantia_gpio_cnt = -1, node; + int res = -1; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) { + aquantia_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_gpio_cnt", -1); + if (aquantia_gpio_cnt >= 1) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "aquantia_gpio", + (u32 *)aquantia_gpio, aquantia_gpio_cnt); + if (res >= 0) + return aquantia_gpio_cnt; + } + } + + return res; +} + +int get_qca808x_gpio(int qca808x_gpio[2]) +{ + int qca808x_gpio_cnt = -1, node; + int res = -1; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) { + qca808x_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "qca808x_gpio_cnt", -1); + if (qca808x_gpio_cnt >= 1) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "qca808x_gpio", + (u32 *)qca808x_gpio, qca808x_gpio_cnt); + if (res >= 0) + return qca808x_gpio_cnt; + } + } + + return res; +} + +void aquantia_phy_reset_init(void) +{ + int aquantia_gpio[2] = {-1, -1}, aquantia_gpio_cnt, i; + unsigned int *aquantia_gpio_base; + uint32_t cfg; + + if (!aq_phy_initialised) { + aquantia_gpio_cnt = get_aquantia_gpio(aquantia_gpio); + if (aquantia_gpio_cnt >= 1) { + for (i = 0; i < aquantia_gpio_cnt; i++) { + if (aquantia_gpio[i] >= 0) { + aquantia_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(aquantia_gpio[i]); + cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP; + writel(cfg, aquantia_gpio_base); + } + } + } + aq_phy_initialised = 1; + } +} + +void qca808x_phy_reset_init(void) +{ + int qca808x_gpio[2] = {-1, -1}, qca808x_gpio_cnt, i; + unsigned int *qca808x_gpio_base; + uint32_t cfg; + + qca808x_gpio_cnt = get_qca808x_gpio(qca808x_gpio); + if (qca808x_gpio_cnt >= 1) { + for (i = 0; i < qca808x_gpio_cnt; i++) { + if (qca808x_gpio[i] >= 0) { + qca808x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca808x_gpio[i]); + cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP; + writel(cfg, qca808x_gpio_base); + } + } + } +} + +void aquantia_phy_reset_init_done(void) +{ + int aquantia_gpio[2] = {-1, -1}, aquantia_gpio_cnt, i; + + aquantia_gpio_cnt = get_aquantia_gpio(aquantia_gpio); + if (aquantia_gpio_cnt >= 1) { + for (i = 0; i < aquantia_gpio_cnt; i++) + gpio_set_value(aquantia_gpio[i], 0x1); + } +} + +void qca808x_phy_reset_init_done(void) +{ + int qca808x_gpio[2] = {-1, -1}, qca808x_gpio_cnt, i; + + qca808x_gpio_cnt = get_qca808x_gpio(qca808x_gpio); + if (qca808x_gpio_cnt >= 1) { + for (i = 0; i < qca808x_gpio_cnt; i++) + gpio_set_value(qca808x_gpio[i], 0x1); + } +} + +void bring_phy_out_of_reset(void) +{ + aquantia_phy_reset_init(); + qca808x_phy_reset_init(); + mdelay(500); + aquantia_phy_reset_init_done(); + qca808x_phy_reset_init_done(); + mdelay(500); +} + void devsoc_eth_initialize(void) { eth_clock_init(); + + set_function_select_as_mdc_mdio(); + + bring_phy_out_of_reset(); } int board_eth_init(bd_t *bis) diff --git a/board/qca/arm/devsoc/devsoc.h b/board/qca/arm/devsoc/devsoc.h index 655852d7f5..2436060ae3 100644 --- a/board/qca/arm/devsoc/devsoc.h +++ b/board/qca/arm/devsoc/devsoc.h @@ -104,8 +104,6 @@ extern const add_node_t add_fdt_node[]; /* * weak function */ -__weak void aquantia_phy_reset_init_done(void) {} -__weak void aquantia_phy_reset_init(void) {} __weak void qgic_init(void) {} __weak void handle_noc_err(void) {} __weak void board_pcie_clock_init(int id) {} @@ -145,6 +143,27 @@ enum pcie_port_lane_mode_t{ #define PCIE_1_CLOCK_DISABLE_BIT 12 #define PCIE_2_CLOCK_DISABLE_BIT 10 +/* + * GPIO functional configs + */ +#define GPIO_DRV_2_MA 0x0 << 6 +#define GPIO_DRV_4_MA 0x1 << 6 +#define GPIO_DRV_6_MA 0x2 << 6 +#define GPIO_DRV_8_MA 0x3 << 6 +#define GPIO_DRV_10_MA 0x4 << 6 +#define GPIO_DRV_12_MA 0x5 << 6 +#define GPIO_DRV_14_MA 0x6 << 6 +#define GPIO_DRV_16_MA 0x7 << 6 + +#define GPIO_OE 0x1 << 9 + +#define GPIO_NO_PULL 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_KEEPER 0x2 +#define GPIO_PULL_UP 0x3 + +#define MDC_MDIO_FUNC_SEL 0x1 << 2 + /* * SMEM */