From 0f7bd25186177886bcb6cebd02b9dd6c3a50a19d Mon Sep 17 00:00:00 2001
From: Timple Raj M <quic_timple@quicinc.com>
Date: Tue, 16 May 2023 17:33:54 +0530
Subject: [PATCH] arm: dts: ipq5332: Add AP-MI01.9 RDP Support

The AP-MI01.9 is similar to AP-MI01.2 with internal
radio disabled and pcie0 for WKK 5G and pcie1 for WKK 2G

Change-Id: I568c4da0c7604881395dad08be42201fdf9c746b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
---
 arch/arm/dts/Makefile           |   1 +
 arch/arm/dts/ipq5332-mi01.9.dts | 235 ++++++++++++++++++++++++++++++++
 2 files changed, 236 insertions(+)
 create mode 100644 arch/arm/dts/ipq5332-mi01.9.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4f8670a379..c289d54be2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-emulation.dtb \
 				ipq5332-mi01.3.dtb \
 				ipq5332-mi01.4.dtb \
 				ipq5332-mi01.6.dtb \
+				ipq5332-mi01.9.dtb \
 				ipq5332-mi03.1.dtb \
 				ipq5332-mi04.1.dtb \
 				ipq5332-db-mi01.1.dtb \
diff --git a/arch/arm/dts/ipq5332-mi01.9.dts b/arch/arm/dts/ipq5332-mi01.9.dts
new file mode 100644
index 0000000000..b4f22a8870
--- /dev/null
+++ b/arch/arm/dts/ipq5332-mi01.9.dts
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "ipq5332-soc.dtsi"
+/ {
+	machid = <0x8060006>;
+	config_name = "config@mi01.9";
+
+	aliases {
+		console = "/serial@78AF000";
+		nand = "/nand-controller@79B0000";
+		mmc = "/sdhci@7804000";
+		usb0 = "/xhci@8a00000";
+		i2c0 = "/i2c@78B6000";
+		pci0 = "/pci@20000000";
+		pci1 = "/pci@18000000";
+	};
+
+	serial@78AF000 {
+		status = "ok";
+		serial_gpio {
+			blsp0_uart_rx {
+				gpio = <18>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			blsp0_uart_tx {
+				gpio = <19>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	i2c@78B6000 {
+		i2c_gpio {
+			gpio1 {
+				gpio = <29>;
+				func = <3>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+				oe = <GPIO_OE_ENABLE>;
+			};
+
+			gpio2 {
+				gpio = <30>;
+				func = <3>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+				oe = <GPIO_OE_ENABLE>;
+			};
+		};
+	};
+
+	nand: nand-controller@79B0000 {
+		nand_gpio {
+			qspi_dat3 {
+				gpio = <8>;
+				func = <2>;
+				pull = <GPIO_PULL_DOWN>;
+				drvstr = <GPIO_8MA>;
+			};
+			qspi_dat2 {
+				gpio = <9>;
+				func = <2>;
+				pull = <GPIO_PULL_DOWN>;
+				drvstr = <GPIO_8MA>;
+			};
+			qspi_dat1 {
+				gpio = <10>;
+				func = <2>;
+				pull = <GPIO_PULL_DOWN>;
+				drvstr = <GPIO_8MA>;
+			};
+			qspi_dat0 {
+				gpio = <11>;
+				func = <2>;
+				pull = <GPIO_PULL_DOWN>;
+				drvstr = <GPIO_8MA>;
+			};
+			qspi_cs_n {
+				gpio = <12>;
+				func = <2>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			qspi_clk {
+				gpio = <13>;
+				func = <2>;
+				pull = <GPIO_PULL_DOWN>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	mmc: sdhci@7804000 {
+		mmc_gpio {
+			emmc_dat3 {
+				gpio = <8>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			emmc_dat2 {
+				gpio = <9>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			emmc_dat1 {
+				gpio = <10>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			emmc_dat0 {
+				gpio = <11>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			emmc_cmd{
+				gpio = <12>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_8MA>;
+			};
+			emmc_clk{
+				gpio = <13>;
+				func = <1>;
+				pull = <GPIO_NO_PULL>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	pci0: pci@20000000 {
+		status = "ok";
+		perst_gpio = <38>;
+		lane = <1>;
+		pci_gpio {
+			pci_rst {
+				gpio = <38>;
+				pull = <GPIO_PULL_UP>;
+				oe = <GPIO_OE_ENABLE>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	pci1: pci@18000000 {
+		status = "ok";
+		perst_gpio = <47>;
+		lane = <2>;
+		pci_gpio {
+			pci_rst {
+				gpio = <47>;
+				pull = <GPIO_PULL_UP>;
+				oe = <GPIO_OE_ENABLE>;
+				drvstr = <GPIO_8MA>;
+			};
+		};
+	};
+
+	ess-switch {
+		switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
+		switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
+		qca808x_gpio = <51>;
+		qca808x_gpio_cnt = <1>;
+		qca8084_switch_enable = <1>;
+
+		port_phyinfo {
+			port@0 {
+				phy_address = <1>;
+				uniphy_id = <0>;
+				phy_type = <QCA8084_PHY_TYPE>;
+				uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
+			};
+			port@1 {
+				phy_type = <SFP_PHY_TYPE>;
+				uniphy_id = <1>;
+				uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
+			};
+		};
+
+		qca8084_swt_info {
+			switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
+			switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
+
+			port@0 {
+				phy_address = <0xff>;
+				phy_type = <UNUSED_PHY_TYPE>;
+				forced-speed = <2500>;
+				forced-duplex = <1>;
+			};
+			port@1 {
+				phy_address = <1>;
+				phy_type = <QCA8084_PHY_TYPE>;
+			};
+			port@2 {
+				phy_address = <2>;
+				phy_type = <QCA8084_PHY_TYPE>;
+			};
+			port@3 {
+				phy_address = <3>;
+				phy_type = <QCA8084_PHY_TYPE>;
+			};
+			port@4 {
+				phy_address = <0x4>;
+				phy_type = <QCA8084_PHY_TYPE>;
+			};
+			port@5 {
+				phy_address = <0xff>;
+				phy_type = <UNUSED_PHY_TYPE>;
+				forced-speed = <2500>;
+				forced-duplex = <1>;
+			};
+		};
+	};
+};