From 09f2298093dc6c3c7182f536e39745b57d62fd5f Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Mon, 22 Jun 2020 14:15:56 +0530 Subject: [PATCH 1/2] ipq5018: Add mp03.1 support in tiny U-boot This changes add mp03.1(Ap & Db) support in tiny u-boot for 16MB profile Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: If27bcb8f760c2e648b70811576fc62c4a44f249b --- arch/arm/dts/Makefile | 4 +++- arch/arm/dts/ipq5018-db-mp02.1.dts | 1 + arch/arm/dts/ipq5018-mp02.1.dts | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2ea1889680..d5f4568560 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-emulation.dtb \ ipq5018-mp03.1.dtb else dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-db-mp02.1.dtb \ - ipq5018-mp02.1.dtb + ipq5018-mp02.1.dtb \ + ipq5018-mp03.1.dtb \ + ipq5018-db-mp03.1.dtb endif dtb-$(CONFIG_ARCH_IPQ6018) += ipq6018-cp01-c1.dtb \ diff --git a/arch/arm/dts/ipq5018-db-mp02.1.dts b/arch/arm/dts/ipq5018-db-mp02.1.dts index 3de8fa8ea8..308d33e2a8 100644 --- a/arch/arm/dts/ipq5018-db-mp02.1.dts +++ b/arch/arm/dts/ipq5018-db-mp02.1.dts @@ -17,6 +17,7 @@ model ="QCA, IPQ5018/DB-MP02.1"; compatible = "qca,ipq5018", "qca,ipq5018-db-mp02.1"; machid = <0x1040003>; + config_name = "config@db-mp02.1"; config_name = "config@1"; aliases { diff --git a/arch/arm/dts/ipq5018-mp02.1.dts b/arch/arm/dts/ipq5018-mp02.1.dts index ac94a434f2..3c3fbc30f9 100644 --- a/arch/arm/dts/ipq5018-mp02.1.dts +++ b/arch/arm/dts/ipq5018-mp02.1.dts @@ -17,6 +17,7 @@ model ="QCA, IPQ5018-MP02.1"; compatible = "qca,ipq5018", "qca,ipq5018-mp02.1"; machid = <0x8040000>; + config_name = "config@mp02.1"; config_name = "config@1"; aliases { From 65b179ddc46f6479dc84025ace689a29c5914f19 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Mon, 1 Jun 2020 11:00:02 +0530 Subject: [PATCH 2/2] ipq5018: Update pcie phy initialization Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: Ia5228bffd2b663e463542f2c96012329eefb1833 --- arch/arm/dts/ipq5018-db-mp03.1.dts | 7 +- arch/arm/dts/ipq5018-db-mp03.3.dts | 13 +- arch/arm/dts/ipq5018-mp03.1.dts | 8 +- arch/arm/dts/ipq5018-mp03.3.dts | 14 +- arch/arm/dts/ipq5018-soc.dtsi | 14 +- board/qca/arm/ipq5018/ipq5018.c | 283 ++++++++++++++++++++++------- board/qca/arm/ipq5018/ipq5018.h | 25 ++- include/configs/ipq5018.h | 5 +- 8 files changed, 280 insertions(+), 89 deletions(-) diff --git a/arch/arm/dts/ipq5018-db-mp03.1.dts b/arch/arm/dts/ipq5018-db-mp03.1.dts index 1e735f503f..22ce6763bd 100644 --- a/arch/arm/dts/ipq5018-db-mp03.1.dts +++ b/arch/arm/dts/ipq5018-db-mp03.1.dts @@ -25,8 +25,7 @@ i2c0 = "/i2c@78b6000"; gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; - pci0 = "/pci@80000000"; - pci1 = "/pci@a0000000"; + pci0 = "/pci@a0000000"; nand = "/nand-controller@79B0000"; }; @@ -96,8 +95,10 @@ }; }; - pci0: pci@80000000 { + pci0: pci@a0000000 { status = "ok"; + perst_gpio = <15>; + mode = "fixed"; pci_gpio { pci_rst { gpio = <15>; diff --git a/arch/arm/dts/ipq5018-db-mp03.3.dts b/arch/arm/dts/ipq5018-db-mp03.3.dts index 3fbdb8d83b..f4af216c11 100644 --- a/arch/arm/dts/ipq5018-db-mp03.3.dts +++ b/arch/arm/dts/ipq5018-db-mp03.3.dts @@ -26,6 +26,7 @@ gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; pci0 = "/pci@80000000"; + pci1 = "/pci@a0000000"; nand = "/nand-controller@79B0000"; }; @@ -89,10 +90,14 @@ pci0: pci@80000000 { status = "ok"; + perst_gpio = <18>; + mode = "fixed"; pci_gpio { pci_rst { - gpio = <15>; + gpio = <18>; func = <0>; + pull = ; + oe = ; od_en = ; drvstr = ; }; @@ -101,10 +106,14 @@ pci1: pci@a0000000 { status = "ok"; + perst_gpio = <15>; + mode = "fixed"; pci_gpio { pci_rst { - gpio = <18>; + gpio = <15>; func = <0>; + pull = ; + oe = ; od_en = ; drvstr = ; }; diff --git a/arch/arm/dts/ipq5018-mp03.1.dts b/arch/arm/dts/ipq5018-mp03.1.dts index 5e3359e506..5072b7bbff 100644 --- a/arch/arm/dts/ipq5018-mp03.1.dts +++ b/arch/arm/dts/ipq5018-mp03.1.dts @@ -25,7 +25,7 @@ i2c0 = "/i2c@78b6000"; gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; - pci1 = "/pci@a0000000"; + pci0 = "/pci@a0000000"; nand = "/nand-controller@79B0000"; }; @@ -95,11 +95,13 @@ }; }; - pci1: pci@a0000000 { + pci0: pci@a0000000 { status = "ok"; + perst_gpio = <15>; + mode = "fixed"; pci_gpio { pci_rst { - gpio = <18>; + gpio = <15>; func = <0>; pull = ; oe = ; diff --git a/arch/arm/dts/ipq5018-mp03.3.dts b/arch/arm/dts/ipq5018-mp03.3.dts index 12d0df0830..d130fda8bf 100644 --- a/arch/arm/dts/ipq5018-mp03.3.dts +++ b/arch/arm/dts/ipq5018-mp03.3.dts @@ -26,7 +26,7 @@ gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; pci0 = "/pci@80000000"; - pcie1 = "/pci@a0000000"; + pci1 = "/pci@a0000000"; nand = "/nand-controller@79B0000"; }; @@ -96,10 +96,14 @@ pci0: pci@80000000 { status = "ok"; + perst_gpio = <18>; + mode = "fixed"; pci_gpio { pci_rst { - gpio = <15>; + gpio = <18>; func = <0>; + pull = ; + oe = ; od_en = ; drvstr = ; }; @@ -108,10 +112,14 @@ pci1: pci@a0000000 { status = "ok"; + perst_gpio = <15>; + mode = "fixed"; pci_gpio { pci_rst { - gpio = <18>; + gpio = <15>; func = <0>; + pull = ; + oe = ; od_en = ; drvstr = ; }; diff --git a/arch/arm/dts/ipq5018-soc.dtsi b/arch/arm/dts/ipq5018-soc.dtsi index e139a29964..5100426b70 100644 --- a/arch/arm/dts/ipq5018-soc.dtsi +++ b/arch/arm/dts/ipq5018-soc.dtsi @@ -121,13 +121,13 @@ 0x80300000 0xd00000 0x80100000 0x100000 0x01875004 0x40 - 0x84000 0x1000>; + 0x7e000 0x800>; reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars", "axi_conf", "pci_rst", "pci_phy"; - perst_gpio = <27>; gen3 = <1>; + lane = <1>; status = "disabled"; - skip_phy_init = <1>; + skip_phy_int = <1>; }; pci@a0000000 { @@ -140,13 +140,13 @@ 0xa0001000 0x1000 0xa0300000 0xd00000 0xa0100000 0x100000 - 0x01875004 0x40 - 0x84000 0x1000>; + 0x01876004 0x40 + 0x86000 0x1000>; reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars", "axi_conf", "pci_rst", "pci_phy"; - perst_gpio = <28>; gen3 = <1>; + lane = <2>; status = "disabled"; - skip_phy_init = <1>; + skip_phy_int = <1>; }; }; diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index 138210f9e8..76e24d5fec 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -1267,95 +1267,103 @@ int ipq_board_usb_init(void) #endif #ifdef CONFIG_PCI_IPQ -static void pcie_v2_clock_init(int id) +static void pcie_v2_clock_init(int lane) { #ifdef CONFIG_PCI - int cfg; - unsigned tmp; + u32 reg_val; void __iomem *base; /*single lane*/ - if (id == 0) { + /* Enable SYS_NOC clock */ + if (lane == 1) { base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; + writel(CLK_ENABLE, GCC_SYS_NOC_PCIE1_AXI_CBCR); + mdelay(100); /* Configure pcie1_aux_clk_src */ - cfg = (GCC_PCIE1_AUX_CFG_RCGR_SRC_SEL | - GCC_PCIE1_AUX_CFG_RCGR_SRC_DIV); + writel((GCC_PCIE1_AUX_CFG_RCGR_SRC_SEL | + GCC_PCIE1_AUX_CFG_RCGR_SRC_DIV), + base + PCIE_AUX_CFG_RCGR); + mdelay(100); + reg_val = readl(base + PCIE_AUX_CMD_RCGR); + reg_val &= ~0x1; + reg_val |= 0x1; + writel(reg_val, base + PCIE_AUX_CMD_RCGR); + + /* Configure pcie1_axi_clk_src */ + writel((GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL | + GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV), + base + PCIE_AXI_CFG_RCGR); + mdelay(100); + reg_val = readl(base + PCIE_AXI_CMD_RCGR); + reg_val &= ~0x1; + reg_val |= 0x1; + writel(reg_val, base + PCIE_AXI_CMD_RCGR); } else { /*double lane*/ base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; - /* Configure pcie0_aux_clk_src */ - cfg = (GCC_PCIE0_AUX_CFG_RCGR_SRC_SEL | - GCC_PCIE0_AUX_CFG_RCGR_SRC_DIV); - } - - writel(cfg, base + PCIE_AUX_CFG_RCGR); - writel(CMD_UPDATE, base + PCIE_AUX_CMD_RCGR); - mdelay(100); - writel(ROOT_EN, base + PCIE_AUX_CMD_RCGR); - - if (id == 0) - /* Configure pcie1_axi_clk_src */ - cfg = (GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL | - GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV); - - else - /* Configure pcie0_axi_clk_src */ - cfg = (GCC_PCIE0_AXI_CFG_RCGR_SRC_SEL | - GCC_PCIE0_AXI_CFG_RCGR_SRC_DIV); - - writel(cfg, base + PCIE_AXI_CFG_RCGR); - writel(CMD_UPDATE, base + PCIE_AXI_CMD_RCGR); - mdelay(100); - writel(ROOT_EN, base + PCIE_AXI_CMD_RCGR); - - /* Configure CBCRs */ - if (id == 0) - writel(CLK_ENABLE, GCC_SYS_NOC_PCIE1_AXI_CBCR); - else writel(CLK_ENABLE, GCC_SYS_NOC_PCIE0_AXI_CBCR); + mdelay(100); + /* Configure pcie1_aux_clk_src */ + writel((GCC_PCIE0_AUX_CFG_RCGR_SRC_SEL | + GCC_PCIE0_AUX_CFG_RCGR_SRC_DIV), + base + PCIE_AUX_CFG_RCGR); + mdelay(100); + reg_val = readl(base + PCIE_AUX_CMD_RCGR); + reg_val &= ~0x1; + reg_val |= 0x1; + writel(reg_val, base + PCIE_AUX_CMD_RCGR); + /* Configure pcie1_axi_clk_src */ + writel((GCC_PCIE0_AXI_CFG_RCGR_SRC_SEL | + GCC_PCIE0_AXI_CFG_RCGR_SRC_DIV), + base + PCIE_AXI_CFG_RCGR); + mdelay(100); + reg_val = readl(base + PCIE_AXI_CMD_RCGR); + reg_val &= ~0x1; + reg_val |= 0x1; + writel(reg_val, base + PCIE_AXI_CMD_RCGR); + } + mdelay(50); + reg_val= readl(base + PCIE_AXI_M_CBCR); + reg_val |= CLK_ENABLE; + writel(reg_val, base + PCIE_AXI_M_CBCR); + + mdelay(50); + reg_val = readl(base + PCIE_AXI_S_CBCR); + reg_val |= CLK_ENABLE; + writel(reg_val, base + PCIE_AXI_S_CBCR); + + mdelay(50); writel(CLK_ENABLE, base + PCIE_AHB_CBCR); - tmp = readl(base + PCIE_AXI_M_CBCR); - tmp |= CLK_ENABLE; - writel(tmp, base + PCIE_AXI_M_CBCR); - - tmp = readl(base + PCIE_AXI_S_CBCR); - tmp |= CLK_ENABLE; - writel(tmp, base + PCIE_AXI_S_CBCR); - + mdelay(50); writel(CLK_ENABLE, base + PCIE_AUX_CBCR); - tmp = readl(base + PCIE_PIPE_CBCR); - tmp |= CLK_ENABLE; - writel(tmp, base + PCIE_PIPE_CBCR); + mdelay(50); + writel(CLK_ENABLE, base + PCIE_AXI_S_BRIDGE_CBCR); - writel(CLK_ENABLE, PCIE_AXI_S_BRIDGE_CBCR); + mdelay(50); + reg_val= readl(base + PCIE_PIPE_CBCR); + reg_val |= CLK_ENABLE; + writel(reg_val, base + PCIE_PIPE_CBCR); + mdelay(50); #endif return; } -static void pcie_v2_clock_deinit(int id) +static void pcie_v2_clock_deinit(int lane) { #ifdef CONFIG_PCI void __iomem *base; /*single lane*/ - if (id == 0) + if (lane == 1) { base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; - else /*double lane*/ - base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; - - writel(0x0, base + PCIE_AUX_CFG_RCGR); - writel(0x0, base + PCIE_AUX_CMD_RCGR); - writel(0x0, base + PCIE_AXI_CFG_RCGR); - writel(0x0, base + PCIE_AXI_CMD_RCGR); - mdelay(100); - - if (id == 0) writel(0x0, GCC_SYS_NOC_PCIE1_AXI_CBCR); - else + } else { /*double lane*/ + base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; writel(0x0, GCC_SYS_NOC_PCIE0_AXI_CBCR); - + } + mdelay (50); writel(0x0, base + PCIE_AHB_CBCR); writel(0x0, base + PCIE_AXI_M_CBCR); writel(0x0, base + PCIE_AXI_S_CBCR); @@ -1366,10 +1374,136 @@ static void pcie_v2_clock_deinit(int id) return; } +static void pcie_phy_init(u32 reg_base, int mode, int lane) +{ + for (int i = 0; i < lane; ++i) { + /*set frequency initial value*/ + writel(0x1cb9, (reg_base + (i * 0x800)) + SSCG_CTRL_REG_4); + writel(0x023a, (reg_base + (i * 0x800)) + SSCG_CTRL_REG_5); + /*set spectrum spread count*/ + writel(0x1360, (reg_base + (i * 0x800)) + SSCG_CTRL_REG_3); + if (mode == 1) { + /*set fstep*/ + writel(0x0, (reg_base + (i * 0x800)) + + SSCG_CTRL_REG_1); + writel(0x0, (reg_base + (i * 0x800)) + + SSCG_CTRL_REG_2); + } else { + /*set fstep*/ + writel(0x1, (reg_base + (i * 0x800)) + + SSCG_CTRL_REG_1); + writel(0xeb, (reg_base + (i * 0x800)) + + SSCG_CTRL_REG_2); + /*set FLOOP initial value*/ + writel(0x3f9, (reg_base + (i * 0x800)) + + CDR_CTRL_REG_4); + writel(0x1c9, (reg_base + (i * 0x800)) + + CDR_CTRL_REG_5); + /*set upper boundary level*/ + writel(0x419, (reg_base + (i * 0x800)) + + CDR_CTRL_REG_2); + /*set fixed offset*/ + writel(0x200, (reg_base + (i * 0x800)) + + CDR_CTRL_REG_1); + } + } +} + +static void pcie_reset(int lane) +{ + u32 reg_val; + void __iomem *base; + + /*single lane*/ + if (lane == 1) + base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; + else /*double lane*/ + base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; + + reg_val = readl(base + PCIE_BCR); + writel(reg_val | GCC_PCIE_BCR_ENABLE, + (base + PCIE_BCR)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_BCR_ENABLE), + (base + PCIE_BCR)); + + reg_val = readl(base + PCIE_PHY_BCR); + writel(reg_val | GCC_PCIE_BLK_ARES, + (base + PCIE_PHY_BCR)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_BLK_ARES), + (base + PCIE_PHY_BCR)); + + reg_val = readl(base + PCIE_PHY_PHY_BCR); + writel(reg_val | GCC_PCIE_BLK_ARES, + (base + PCIE_PHY_PHY_BCR)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_BLK_ARES), + (base + PCIE_PHY_PHY_BCR)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_PIPE_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_PIPE_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_SLEEP_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_SLEEP_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_CORE_STICKY_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_CORE_STICKY_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_AXI_MASTER_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_AXI_MASTER_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_AXI_SLAVE_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_AXI_SLAVE_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCIE_AHB_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCIE_AHB_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCI_AXI_MASTER_STICKY_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCI_AXI_MASTER_STICKY_ARES), + (base + PCIE_MISC_RESET)); + + reg_val = readl(base + PCIE_MISC_RESET); + writel(reg_val | GCC_PCI_AXI_SLAVE_STICKY_ARES, + (base + PCIE_MISC_RESET)); + mdelay(20); + writel(reg_val & (~GCC_PCI_AXI_SLAVE_STICKY_ARES), + (base + PCIE_MISC_RESET)); +} + void board_pci_init(int id) { - int node, gpio_node; + int node, gpio_node, mode = 0; + struct fdt_resource pci_phy; char name[16]; + int err, lane; snprintf(name, sizeof(name), "pci%d", id); node = fdt_path_offset(gd->fdt_blob, name); @@ -1377,17 +1511,31 @@ void board_pci_init(int id) printf("Could not find PCI in device tree\n"); return; } + + err = fdt_get_named_resource(gd->fdt_blob, node, + "reg", "reg-names", "pci_phy",&pci_phy); + if (err < 0) + return; + + if (!strcmp(fdt_getprop(gd->fdt_blob, node, "mode", NULL), "fixed")){ + mode = 1; + } + lane = fdtdec_get_int(gd->fdt_blob, node, "lane", 0); + gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio"); if (gpio_node >= 0) qca_gpio_init(gpio_node); - pcie_v2_clock_init(id); + pcie_reset(lane); + pcie_v2_clock_init(lane); + pcie_phy_init(pci_phy.start, mode, lane); + return; } void board_pci_deinit() { - int node, gpio_node, i, err; + int node, gpio_node, i, lane, err; char name[16]; struct fdt_resource parf; struct fdt_resource pci_phy; @@ -1397,7 +1545,7 @@ void board_pci_deinit() node = fdt_path_offset(gd->fdt_blob, name); if (node < 0) { printf("Could not find PCI in device tree\n"); - return; + continue; } err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "parf", &parf); @@ -1406,7 +1554,7 @@ void board_pci_deinit() err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "pci_phy", &pci_phy); if (err < 0) - return; + continue; writel(0x1, pci_phy.start + 800); writel(0x0, pci_phy.start + 804); @@ -1414,7 +1562,8 @@ void board_pci_deinit() if (gpio_node >= 0) qca_gpio_deinit(gpio_node); - pcie_v2_clock_deinit(i); + lane = fdtdec_get_int(gd->fdt_blob, node, "lane", 0); + pcie_v2_clock_deinit(lane); } return ; diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index bf62e9b560..1013e350e1 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -341,6 +341,17 @@ #define GCC_SYS_NOC_PCIE0_AXI_CBCR 0x01826048 #define GCC_SYS_NOC_PCIE1_AXI_CBCR 0x0182604C +#define GCC_PCIE_BCR_ENABLE (1 << 0) +#define GCC_PCIE_BLK_ARES (1 << 0) +#define GCC_PCIE_PIPE_ARES (1 << 0) +#define GCC_PCIE_SLEEP_ARES (1 << 1) +#define GCC_PCIE_CORE_STICKY_ARES (1 << 2) +#define GCC_PCIE_AXI_MASTER_ARES (1 << 3) +#define GCC_PCIE_AXI_SLAVE_ARES (1 << 4) +#define GCC_PCIE_AHB_ARES (1 << 5) +#define GCC_PCI_AXI_MASTER_STICKY_ARES (1 << 6) +#define GCC_PCI_AXI_SLAVE_STICKY_ARES (1 << 7) + #define GCC_PCIE0_BOOT_CLOCK_CTL 0x01875000 #define GCC_PCIE0_BCR 0x01875004 #define GCC_PCIE0_AXI_M_CBCR 0x01875008 @@ -387,6 +398,7 @@ #define GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL (1 << 8) #define GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV 0x7 +#define PCIE_BCR 0x4 #define PCIE_AXI_M_CBCR 0x8 #define PCIE_AXI_S_CBCR 0xC #define PCIE_AHB_CBCR 0x10 @@ -394,6 +406,9 @@ #define PCIE_PIPE_CBCR 0x18 #define PCIE_AUX_CMD_RCGR 0x20 #define PCIE_AUX_CFG_RCGR 0x24 +#define PCIE_PHY_BCR 0x38 +#define PCIE_PHY_PHY_BCR 0x3c +#define PCIE_MISC_RESET 0x40 #define PCIE_AXI_S_BRIDGE_CBCR 0x48 #define PCIE_AXI_CMD_RCGR 0x50 #define PCIE_AXI_CFG_RCGR 0x54 @@ -412,13 +427,21 @@ #define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3) #define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4) -#define CLK_ENABLE 0x1 +#define CLK_ENABLE 0x1 + #define SSCG_CTRL_REG_1 0x9c #define SSCG_CTRL_REG_2 0xa0 #define SSCG_CTRL_REG_3 0xa4 #define SSCG_CTRL_REG_4 0xa8 #define SSCG_CTRL_REG_5 0xac #define SSCG_CTRL_REG_6 0xb0 +#define CDR_CTRL_REG_1 0x80 +#define CDR_CTRL_REG_2 0x84 +#define CDR_CTRL_REG_3 0x88 +#define CDR_CTRL_REG_4 0x8C +#define CDR_CTRL_REG_5 0x90 +#define CDR_CTRL_REG_6 0x94 +#define CDR_CTRL_REG_7 0x98 #define USB_PHY_CFG0 0x94 #define USB_PHY_UTMI_CTRL5 0x50 diff --git a/include/configs/ipq5018.h b/include/configs/ipq5018.h index 883a7ba83c..02400375ff 100644 --- a/include/configs/ipq5018.h +++ b/include/configs/ipq5018.h @@ -18,7 +18,6 @@ #include #endif -#define IPQ5018_EMULATION #define CONFIG_IPQ5018 #undef CONFIG_QCA_DISABLE_SCM #define CONFIG_SPI_FLASH_CYPRESS @@ -264,8 +263,8 @@ extern loff_t board_env_size; /* * PCIE Enable */ -#define PCI_MAX_DEVICES 1 -#if defined(CONFIG_PCI_IPQ) && !defined(IPQ5018_EMULATION) +#define PCI_MAX_DEVICES 2 +#if defined(CONFIG_PCI_IPQ) #define CONFIG_PCI #define CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW