diff --git a/board/qca/arm/common/board_init.c b/board/qca/arm/common/board_init.c
index 19f1bf6a51..ca6fafd452 100644
--- a/board/qca/arm/common/board_init.c
+++ b/board/qca/arm/common/board_init.c
@@ -343,12 +343,12 @@ void report_l2err(u32 l2esr)
 }
 #endif
 
-void enable_caches(void)
+__weak void enable_caches(void)
 {
 	icache_enable();
 }
 
-void disable_caches(void)
+__weak void disable_caches(void)
 {
 	icache_disable();
 }
diff --git a/board/qca/arm/ipq806x/ipq806x.c b/board/qca/arm/ipq806x/ipq806x.c
index 57fc729601..b23e609ffa 100644
--- a/board/qca/arm/ipq806x/ipq806x.c
+++ b/board/qca/arm/ipq806x/ipq806x.c
@@ -968,3 +968,15 @@ void clear_l2cache_err(void)
         set_l2_indirect_reg(L2ESR_IND_ADDR, val);
 #endif
 }
+
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+
+void disable_caches(void)
+{
+	icache_disable();
+	dcache_disable();
+}
diff --git a/include/configs/ipq806x.h b/include/configs/ipq806x.h
index 06b2f1e6e4..52129cf025 100644
--- a/include/configs/ipq806x.h
+++ b/include/configs/ipq806x.h
@@ -334,7 +334,7 @@ typedef struct {
  * Cache flush and invalidation based on L1 cache, so the cache line
  * size is configured to 64 */
 #define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_SYS_DCACHE_OFF
+/*#define CONFIG_SYS_DCACHE_OFF*/
 
 /* Enabling this flag will report any L2 errors.
  * By default we are disabling it */