mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
qca: ipq: USB support is now DM model
Moved to DM approach to make it more flexible to support AK/DK/HK chipset. Change-Id: I0fded02c97b7ace500df44bbf39285ef6fb58321 Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
This commit is contained in:
Saravanan Jaganathan
parent
d31988fb33
commit
0e20a955c1
10 changed files with 153 additions and 174 deletions
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@ -22,6 +22,8 @@
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aliases {
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console = "/serial@78af000";
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xhci0 = "/xhci@8a00000";
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xhci1 = "/xhci@6000000";
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};
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};
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@ -28,5 +28,21 @@
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gpt_freq_hz = <48000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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xhci@8a00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8a00000 0xcd00>;
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rst_ctrl = <0x181E038 0x4>;
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};
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xhci@6000000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000000 0xcd00>;
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rst_ctrl = <0x181E01C 0x4>;
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};
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};
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@ -21,6 +21,9 @@
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aliases {
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console = "/serial@78af000";
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xhci0 = "/xhci@8a00000";
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xhci1 = "/xhci@8c00000";
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};
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};
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@ -38,6 +38,18 @@
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};
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xhci@8a00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8a00000 0xcd00>;
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};
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xhci@8c00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8c00000 0xcd00>;
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};
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};
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@ -252,9 +252,10 @@ CONFIG_REQUIRE_SERIAL_CONSOLE=y
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# CONFIG_DM_THERMAL is not set
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#
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# TPM support
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# USB support
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#
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# CONFIG_USB is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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#
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# Graphics support
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@ -258,9 +258,10 @@ CONFIG_REQUIRE_SERIAL_CONSOLE=y
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# CONFIG_DM_THERMAL is not set
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#
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# TPM support
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# USB support
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#
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# CONFIG_USB is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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#
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# Graphics support
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@ -63,6 +63,6 @@ obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
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obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
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obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
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obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
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obj-$(CONFIG_IPQ_USB) += xhci-ipq.o
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obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
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# designware
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obj-$(CONFIG_USB_DWC2) += dwc2.o
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@ -20,144 +20,73 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <usb.h>
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#include <linux/compat.h>
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#include <asm-generic/errno.h>
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#include <linux/usb/dwc3.h>
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#include "xhci.h"
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#define IPQ_XHCI_COUNT 0x2
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#define GCC_USB_RST_CTRL_1 0x181E038
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#define GCC_USB_RST_CTRL_2 0x181E01C
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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struct ipq_xhci_platdata {
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fdt_addr_t hcd_base;
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unsigned int rst_ctrl;
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unsigned int hs_only;
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};
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struct ipq_xhci {
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struct ipq_xhci_platdata usb_plat;
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struct xhci_ctrl ctrl;
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struct udevice* dev;
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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unsigned int *gcc_rst_ctrl;
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};
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static struct ipq_xhci ipq[IPQ_XHCI_COUNT];
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int __board_usb_init(int index, enum usb_init_type init)
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void ipq_reset_usb_phy(struct ipq_xhci *ipq)
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{
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return 0;
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}
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unsigned int gcc_rst_ctrl;
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struct ipq_xhci_platdata *platdata;
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int board_usb_init(int index, enum usb_init_type init)
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__attribute__((weak, alias("__board_usb_init")));
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platdata = dev_get_platdata(ipq->dev);
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gcc_rst_ctrl = platdata->rst_ctrl;
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static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
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{
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clrsetbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(mode));
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}
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void ipq_reset_usb_phy(unsigned int *gcc_rst_ctrl)
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{
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/* assert HS PHY POR reset */
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setbits_le32(gcc_rst_ctrl, 0x10);
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mdelay(10);
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/* assert HS PHY SRIF reset */
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setbits_le32(gcc_rst_ctrl, 0x4);
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mdelay(10);
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/* deassert HS PHY SRIF reset and program HS PHY registers */
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clrbits_le32(gcc_rst_ctrl, 0x4);
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mdelay(10);
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/* de-assert USB3 HS PHY POR reset */
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clrbits_le32(gcc_rst_ctrl, 0x10);
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mdelay(10);
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if (gcc_rst_ctrl == (unsigned int*)GCC_USB_RST_CTRL_1) {
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/* assert SS PHY POR reset */
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setbits_le32(gcc_rst_ctrl, 0x20);
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if (gcc_rst_ctrl) {
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/* assert HS PHY POR reset */
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setbits_le32(gcc_rst_ctrl, 0x10);
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mdelay(10);
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/* deassert SS PHY POR reset */
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clrbits_le32(gcc_rst_ctrl, 0x20);
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/* assert HS PHY SRIF reset */
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setbits_le32(gcc_rst_ctrl, 0x4);
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mdelay(10);
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/* deassert HS PHY SRIF reset and program HS PHY registers */
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clrbits_le32(gcc_rst_ctrl, 0x4);
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mdelay(10);
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/* de-assert USB3 HS PHY POR reset */
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clrbits_le32(gcc_rst_ctrl, 0x10);
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mdelay(10);
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if (!platdata->hs_only) {
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/* assert SS PHY POR reset */
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setbits_le32(gcc_rst_ctrl, 0x20);
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mdelay(10);
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/* deassert SS PHY POR reset */
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clrbits_le32(gcc_rst_ctrl, 0x20);
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}
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}
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}
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void dwc3_reset_usb_phy(struct dwc3 *dwc3_reg, unsigned int *gcc_rst_ctrl)
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{
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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mdelay(100);
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ipq_reset_usb_phy(gcc_rst_ctrl);
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mdelay(100);
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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}
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static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg, unsigned int *gcc_rst_ctrl)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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dwc3_reset_usb_phy(dwc3_reg, gcc_rst_ctrl);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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}
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static int dwc3_core_init(struct dwc3 *dwc3_reg, unsigned int *gcc_rst_ctrl)
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{
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u32 reg;
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u32 revision;
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unsigned int dwc3_hwparams1;
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revision = readl(&dwc3_reg->g_snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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puts("this is not a DesignWare USB3 DRD Core\n");
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return -1;
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}
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dwc3_core_soft_reset(dwc3_reg, gcc_rst_ctrl);
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
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reg = readl(&dwc3_reg->g_ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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debug("No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if ((revision & DWC3_REVISION_MASK) < 0x190a)
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reg |= DWC3_GCTL_U2RSTECN;
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writel(reg, &dwc3_reg->g_ctl);
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return 0;
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}
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static int ipq_xhci_core_init(struct ipq_xhci *ipq, unsigned int ipq_base)
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static int ipq_xhci_core_init(struct ipq_xhci *ipq)
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{
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int ret = 0;
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ret = dwc3_core_init(ipq->dwc3_reg, ipq->gcc_rst_ctrl);
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ipq_reset_usb_phy(ipq);
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ret = dwc3_core_init(ipq->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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@ -174,57 +103,78 @@ static void ipq_xhci_core_exit(struct ipq_xhci *ipq)
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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static int xhci_usb_remove(struct udevice *dev)
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{
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struct ipq_xhci *ctx;
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unsigned int ipq_base;
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int ret = 0;
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int ret;
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ret = xhci_deregister(dev);
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if (index >= IPQ_XHCI_COUNT)
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return -1;
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if (index == 0) {
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ctx = &ipq[0];
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ipq_base = IPQ_XHCI_BASE_1;
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ctx->gcc_rst_ctrl = (unsigned int*)GCC_USB_RST_CTRL_1;
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} else {
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ctx = &ipq[1];
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ipq_base = IPQ_XHCI_BASE_2;
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ctx->gcc_rst_ctrl = (unsigned int*)GCC_USB_RST_CTRL_2;
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}
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ctx->hcd = (struct xhci_hccr *)ipq_base;
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret != 0) {
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puts("Failed to initialize board for USB\n");
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debug("%s:xhci deregistration failed\n", __func__);
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return ret;
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}
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ret = ipq_xhci_core_init(ctx, ipq_base);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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ipq_xhci_core_exit(dev_get_priv(dev));
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*hccr = (struct xhci_hccr *)(ipq_base);
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*hcor = (struct xhci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("ipq-xhci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return ret;
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return 0;
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}
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void xhci_hcd_stop(int index)
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static int xhci_usb_probe(struct udevice *dev)
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{
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if (index >= IPQ_XHCI_COUNT) {
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debug("ipq-xhci: index greater than xhci count\n");
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return;
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struct ipq_xhci *context;
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struct ipq_xhci_platdata *platdata;
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struct xhci_hcor *hcor;
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int ret;
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platdata = dev_get_platdata(dev);
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context = dev_get_priv(dev);
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context->hcd = (struct xhci_hccr *)platdata->hcd_base;
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context->dev = dev;
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context->dwc3_reg = (struct dwc3 *)((char *)(context->hcd) + DWC3_REG_OFFSET);
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hcor = (struct xhci_hcor *)((uint32_t)context->hcd +
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HC_LENGTH(xhci_readl(&context->hcd->cr_capbase)));
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ret = ipq_xhci_core_init(context);
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if (ret) {
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puts("Error initializing the XHCI controller\n");
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return -EINVAL;
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}
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ipq_xhci_core_exit(&ipq[index]);
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return xhci_register(dev, context->hcd, hcor);
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}
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static int xhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct ipq_xhci_platdata *platdata;
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const void *blob = gd->fdt_blob;
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platdata = dev_get_platdata(dev);
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platdata->hcd_base = dev_get_addr(dev);
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if (platdata->hcd_base == FDT_ADDR_T_NONE) {
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debug("Error getting DWC3 base address\n");
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return -ENXIO;
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}
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platdata->rst_ctrl = fdtdec_get_int(blob, dev->of_offset, "rst_ctrl", 0);
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platdata->hs_only = fdtdec_get_int(blob, dev->of_offset, "hs_only", 0);
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return 0;
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}
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static const struct udevice_id xhci_match_ids[] = {
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{ .compatible = "qca,dwc3-ipq" },
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{}
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};
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U_BOOT_DRIVER(usb_xhci) = {
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.name = "xhci_ipq",
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.id = UCLASS_USB,
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.of_match = xhci_match_ids,
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.ofdata_to_platdata = xhci_ofdata_to_platdata,
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.probe = xhci_usb_probe,
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.remove = xhci_usb_remove,
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.ops = &xhci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct ipq_xhci_platdata),
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.priv_auto_alloc_size = sizeof(struct ipq_xhci),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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@ -114,18 +114,15 @@ typedef struct {
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* USB Support
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*/
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#define CONFIG_IPQ_USB
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#ifdef CONFIG_IPQ_USB
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#define CONFIG_USB_XHCI_IPQ
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#ifdef CONFIG_USB_XHCI_IPQ
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_CMD_USB
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#define CONFIG_DOS_PARTITION
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define IPQ_XHCI_BASE_1 0x8A00000
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#define IPQ_XHCI_BASE_2 0x6000000
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#endif
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/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
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@ -155,18 +155,15 @@
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/*
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* USB Support
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*/
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#define CONFIG_IPQ_USB
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#ifdef CONFIG_IPQ_USB
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#define CONFIG_USB_XHCI_IPQ
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#ifdef CONFIG_USB_XHCI_IPQ
|
||||
#define CONFIG_USB_XHCI
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#define IPQ_XHCI_BASE_1 0x8A00000
|
||||
#define IPQ_XHCI_BASE_2 0x8C00000
|
||||
|
||||
#endif
|
||||
|
||||
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue