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AU_LINUX_QSDK_FIG_TARGET_ALL.12.0.000.934

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Merge AU_LINUX_QSDK_FIG_TARGET_ALL.12.0.000.934 on remote branch

Change-Id: I7829f0433f1cf5a7d3ae5637874a6cfa44c1d1e4
Signed-off-by: Linux Build Service Account <lnxbuild@localhost>
This commit is contained in:
Linux Build Service Account 2022-01-12 04:19:23 -07:00
commit 0c81b4f57a
14 changed files with 352 additions and 13 deletions
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122
arch/arm/cpu/armv7/qca/common/smem.c
View file

@ -38,6 +38,11 @@
#include "fdt_info.h"
#include <ubi_uboot.h>
#include <command.h>
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#include <sdhci.h>
#include <mmc.h>
#endif
#ifdef IPQ_UBI_VOL_WRITE_SUPPORT
static struct ubi_device *ubi;
@ -145,6 +150,12 @@ static struct smem *smem = (void *)(CONFIG_QCA_SMEM_BASE);
qca_smem_flash_info_t qca_smem_flash_info;
qca_smem_bootconfig_info_t qca_smem_bootconfig_info;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned ipq_runtime_failsafe_status;
unsigned ipq_runtime_fs_skip_status_check = 0;
unsigned ipq_runtime_fs_feature_enabled = 0;
#endif
#ifdef CONFIG_SMEM_VERSION_C
#define SMEM_COMMON_HOST 0xFFFE
@ -496,10 +507,121 @@ int smem_bootconfig_info(void)
return 0;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int smem_runtime_failsafe_info(void)
{
unsigned ret;
ret = smem_read_alloc_entry(SMEM_RUNTIME_FAILSAFE_INFO,
&ipq_runtime_failsafe_status, sizeof(ipq_runtime_failsafe_status));
if (ret != 0) {
printf("\nsmem: Failed to fetch the runtime failsafe status.." \
"Disabling the feature.\n");
ipq_runtime_fs_feature_enabled = 0;
}
if (ipq_runtime_failsafe_status & IPQ_RUNTIME_FAILSAFE_ENABLED) {
printf("\nRuntime Failsafe Feature Enabled\n");
ipq_runtime_fs_feature_enabled = 1;
}
return 0;
}
#endif
#ifndef CONFIG_SDHCI_SUPPORT
extern qca_mmc mmc_host;
#else
extern struct sdhci_host mmc_host;
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int smem_update_bootconfig_to_flash(void)
{
unsigned i, j, len;
uint32_t load_addr = 0;
char *part_name[] = {"0:BOOTCONFIG", "0:BOOTCONFIG1"};
char runcmd[256];
if (smem_runtime_failsafe_info() != 0)
return -ENOMSG;
if (ipq_runtime_fs_feature_enabled == 0)
return 0;
/* Update BOOTCONFIG in flash only if there is an update in SMEM by SBL */
if (!ipq_runtime_fs_skip_status_check) {
if (ipq_runtime_failsafe_status & IPQ_RUNTIME_FS_BOOTCONFIG_UPDATED) {
printf("\nNonHLOS runtime hang detected: Partitions switched.\n");
} else {
return 0;
}
}
if (qca_smem_bootconfig_info.magic_start != _SMEM_DUAL_BOOTINFO_MAGIC_START) {
if(smem_bootconfig_info() != 0)
return -1;
}
fs_debug("\nFailsafe: SMEM bootinfo from SBL: ");
for (j = 0; j < qca_smem_bootconfig_info.numaltpart; j++)
fs_debug("\nPartition: %s primaryboot = %d\n",
qca_smem_bootconfig_info.per_part_entry[j].name,
qca_smem_bootconfig_info.per_part_entry[j].primaryboot);
len = sizeof(part_name)/sizeof(part_name[0]);
load_addr = (uint32_t)&qca_smem_bootconfig_info;
for (i = 0; i < len; i++) {
snprintf(runcmd, sizeof(runcmd), "setenv fileaddr 0x%x && \
setenv filesize %d && flash %s",
load_addr, sizeof(qca_smem_bootconfig_info), part_name[i]);
if (run_command(runcmd, 0) != CMD_RET_SUCCESS)
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
__weak int is_hlos_crashed(void)
{
return 0;
}
void update_hlos_rootfs_primaryboot(void)
{
unsigned int i;
qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
fs_debug("\nFailsafe: %s: HLOS bit is SET", __func__);
printf("\nHLOS runtime hang detected: Switching Partitions.\n");
for (i = 0; i < qca_smem_bootconfig_info.numaltpart; i++) {
if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ||
sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
/* Note: SBL swaps the offsets for NAND case */
if (strncmp("0:HLOS", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)
qca_smem_bootconfig_info.per_part_entry[i].primaryboot = 1;
if (strncmp("rootfs", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)
qca_smem_bootconfig_info.per_part_entry[i].primaryboot = 1;
}
}
ipq_runtime_fs_skip_status_check = 1;
}
#endif
unsigned int get_rootfs_active_partition(void)
{
int i;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled && is_hlos_crashed()) {
update_hlos_rootfs_primaryboot();
smem_update_bootconfig_to_flash();
}
#endif
for (i = 0; i < qca_smem_bootconfig_info.numaltpart; i++) {
if (strncmp("rootfs", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)

2
arch/arm/include/asm/arch-qca-common/qca_common.h
View file

@ -100,6 +100,8 @@ void dump_func(unsigned int dump_level);
int do_dumpqca_flash_data(const char *);
int do_dumpqca_usb_data(unsigned int dump_level);
int apps_iscrashed(void);
int is_hlos_crashed(void);
int ipq_read_tcsr_boot_misc(void);
int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_flag);
int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);

3
arch/arm/include/asm/arch-qca-common/smem.h
View file

@ -127,6 +127,7 @@ typedef struct
extern qca_smem_bootconfig_info_t qca_smem_bootconfig_info;
int smem_bootconfig_info(void);
int smem_update_bootconfig_to_flash(void);
unsigned int get_smem_spi_addr_len(void);
unsigned int get_rootfs_active_partition(void);
unsigned int get_mibib_active_partition(void);
@ -134,4 +135,6 @@ void qca_smem_part_to_mtdparts(char *mtdid, int len);
int ipq_smem_get_socinfo_cpu_type(uint32_t *cpu_type);
int ipq_smem_get_socinfo_version(uint32_t *version);
int ipq_smem_get_boot_flash(uint32_t *flash_type);
int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
uint32_t part_size, uint32_t file_size, char *layout);
#endif

16
arch/arm/lib/bootm.c
View file

@ -33,6 +33,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
extern unsigned ipq_runtime_fs_feature_enabled;
static ulong get_sp(void)
{
@ -277,6 +278,21 @@ struct aarch64_hdr {
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned int cookie, ret;
if (ipq_runtime_fs_feature_enabled) {
cookie = ipq_read_tcsr_boot_misc();
cookie &= ~IPQ_FS_NONHLOS_BIT;
cookie |= IPQ_FS_HLOS_BIT;
fs_debug("\nFailsafe: %s: Clear NonHLOS bit and set HLOS bit\n", __func__);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in setting HLOS failsafe bit\n");
}
#endif
#ifdef CONFIG_ARM64
void (*kernel_entry)(void *fdt_addr, void *res0, void *res1,
void *res2);

8
board/qca/arm/common/fdt_fixup.c
View file

@ -888,6 +888,11 @@ __weak void fdt_fixup_sdx65_gpio(void *blob)
return;
}
__weak void fdt_fixup_runtime_failsafe(void *blob)
{
return;
}
void set_mtdids(void)
{
char mtdids[256];
@ -1047,6 +1052,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_cpus_node(blob);
fdt_low_memory_fixup(blob);
fdt_fixup_qpic(blob);
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
fdt_fixup_runtime_failsafe(blob);
#endif
s = getenv("dload_warm_reset");
if (s)
fdt_fixup_set_dload_warm_reset(blob);

72
board/qca/arm/ipq6018/ipq6018.c
View file

@ -28,9 +28,11 @@
#include <i2c.h>
#include <dm.h>
#include <command.h>
#include <watchdog.h>
#define DLOAD_MAGIC_COOKIE 0x10
#define DLOAD_DISABLED 0x40
#define DLOAD_BITS 0xFF
#define TCSR_SOC_HW_VERSION_REG 0x194D000
@ -45,6 +47,8 @@ const char *del_node[] = {"uboot",
NULL};
const add_node_t add_fdt_node[] = {{}};
static int aq_phy_initialised;
extern unsigned ipq_runtime_fs_feature_enabled;
struct dumpinfo_t dumpinfo_n[] = {
/* TZ stores the DDR physical address at which it stores the
* APSS regs, UTCM copy dump. We will have the TZ IMEM
@ -133,6 +137,31 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
return;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
void fdt_fixup_runtime_failsafe(void *blob)
{
int node_off, ret;
const char *fs_node = {"/soc/qti,scm_restart_reason"};
/* This fixup is for informing HLOS whether
* runtime failsafe feature is enabled or not
*/
node_off = fdt_path_offset(blob, fs_node);
if (node_off < 0) {
printf("%s: Failsafe: unable to find node '%s'\n",
__func__, fs_node);
return;
}
ret = fdt_setprop_u32(blob, node_off, "qti,runtime-failsafe",
ipq_runtime_fs_feature_enabled);
if (ret) {
printf("%s : Unable to set property 'ipq,runtime_failsafe'\n",__func__);
return;
}
}
#endif
int do_pmic_reset()
{
struct udevice *bus, *dev;
@ -167,11 +196,26 @@ int do_pmic_reset()
return 0;
}
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
writel(1, APCS_WDT_RST);
}
#endif
void reset_crashdump(void)
{
unsigned int ret = 0;
unsigned int cookie = 0;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
cookie = ipq_read_tcsr_boot_misc();
fs_debug("\nFailsafe: %s: Clearing DLOAD and NonHLOS bits\n", __func__);
cookie &= ~(DLOAD_BITS);
cookie &= ~(IPQ_FS_NONHLOS_BIT);
#endif
qca_scm_sdi();
ret = qca_scm_dload(CLEAR_MAGIC);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in reseting the Magic cookie\n");
return;
@ -803,11 +847,29 @@ __weak int ipq_get_tz_version(char *version_name, int buf_size)
return 1;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int ipq_read_tcsr_boot_misc(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ6018_DMAGIC_ADDR;
return *dmagic;
}
int is_hlos_crashed(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ6018_DMAGIC_ADDR;
if (*dmagic & IPQ_FS_HLOS_BIT)
return 1;
return 0;
}
#endif
int apps_iscrashed_crashdump_disabled(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ6018_DMAGIC_ADDR;
if (*dmagic == DLOAD_DISABLED)
if (*dmagic & DLOAD_DISABLED)
return 1;
return 0;
@ -817,7 +879,7 @@ int apps_iscrashed(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ6018_DMAGIC_ADDR;
if (*dmagic == DLOAD_MAGIC_COOKIE)
if (*dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;
@ -1383,9 +1445,13 @@ void fdt_fixup_set_qca_cold_reboot_enable(void *blob)
void fdt_fixup_wcss_rproc_for_atf(void *blob)
{
if (fdt_path_offset(blob, "/soc/remoteproc@cd00000") >= 0)
parse_fdt_fixup("/soc/remoteproc@cd00000%qcom,nosecure%1", blob);
else {
parse_fdt_fixup("/soc/qcom_q6v5_wcss@CD00000%qcom,nosecure%1", blob);
parse_fdt_fixup("/soc/qcom_q6v5_wcss@CD00000%qca,wcss-aon-reset-seq%1", blob);
}
}
int get_soc_hw_version(void)
{

7
board/qca/arm/ipq6018/ipq6018.h
View file

@ -263,6 +263,8 @@
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
#define APCS_WDT_RST 0xB017004
unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
unsigned int, unsigned int);
@ -365,9 +367,10 @@ typedef enum {
SMEM_BOOT_DUALPARTINFO = 503,
SMEM_PARTITION_TABLE_OFFSET = 504,
SMEM_SPI_FLASH_ADDR_LEN = 505,
SMEM_RUNTIME_FAILSAFE_INFO = 507,
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
} smem_mem_type_t;
extern const char *rsvd_node;

67
board/qca/arm/ipq9574/ipq9574.c
View file

@ -27,9 +27,11 @@
#include <mmc.h>
#include <sdhci.h>
#include <usb.h>
#include <watchdog.h>
#define DLOAD_MAGIC_COOKIE 0x10
#define DLOAD_DISABLED 0x40
#define DLOAD_BITS 0xFF
DECLARE_GLOBAL_DATA_PTR;
@ -39,6 +41,7 @@ extern int ipq_spi_init(u16);
unsigned int qpic_frequency = 0, qpic_phase = 0;
extern unsigned int qpic_training_offset;
extern unsigned ipq_runtime_fs_feature_enabled;
extern int qca_scm_dpr(u32, u32, void *, size_t);
@ -60,6 +63,31 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
return;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
void fdt_fixup_runtime_failsafe(void *blob)
{
int node_off, ret;
const char *fs_node = {"/soc/qti,scm_restart_reason"};
/* This fixup is for informing HLOS whether
* runtime failsafe feature is enabled or not
*/
node_off = fdt_path_offset(blob, fs_node);
if (node_off < 0) {
printf("%s: Failsafe: unable to find node '%s'\n",
__func__, fs_node);
return;
}
ret = fdt_setprop_u32(blob, node_off, "qti,runtime-failsafe",
ipq_runtime_fs_feature_enabled);
if (ret) {
printf("%s : Unable to set property 'ipq,runtime_failsafe'\n",__func__);
return;
}
}
#endif
void fdt_fixup_qpic(void *blob)
{
int node_off, ret;
@ -1205,11 +1233,26 @@ unsigned long timer_read_counter(void)
return 0;
}
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
writel(1, APCS_WDT_RST);
}
#endif
void reset_crashdump(void)
{
unsigned int ret = 0;
unsigned int cookie = 0;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
cookie = ipq_read_tcsr_boot_misc();
fs_debug("\nFailsafe: %s: Clearing DLOAD and NonHLOS bits\n", __func__);
cookie &= ~(DLOAD_BITS);
cookie &= ~(IPQ_FS_NONHLOS_BIT);
#endif
qca_scm_sdi();
ret = qca_scm_dload(CLEAR_MAGIC);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in reseting the Magic cookie\n");
return;
@ -1311,11 +1354,29 @@ struct dumpinfo_t dumpinfo_s[] = {
};
int dump_entries_s = ARRAY_SIZE(dumpinfo_s);
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int ipq_read_tcsr_boot_misc(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ9574_DMAGIC_ADDR;
return *dmagic;
}
int is_hlos_crashed(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ9574_DMAGIC_ADDR;
if (*dmagic & IPQ_FS_HLOS_BIT)
return 1;
return 0;
}
#endif
int apps_iscrashed_crashdump_disabled(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ9574_DMAGIC_ADDR;
if (*dmagic == DLOAD_DISABLED)
if (*dmagic & DLOAD_DISABLED)
return 1;
return 0;
@ -1325,7 +1386,7 @@ int apps_iscrashed(void)
{
u32 *dmagic = (u32 *)CONFIG_IPQ9574_DMAGIC_ADDR;
if (*dmagic == DLOAD_MAGIC_COOKIE)
if (*dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;

7
board/qca/arm/ipq9574/ipq9574.h
View file

@ -123,6 +123,8 @@
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
#define APCS_WDT_RST 0xB017004
/*
* GCC-QPIC Registers
*/
@ -371,9 +373,10 @@ typedef enum {
SMEM_BOOT_DUALPARTINFO = 503,
SMEM_PARTITION_TABLE_OFFSET = 504,
SMEM_SPI_FLASH_ADDR_LEN = 505,
SMEM_RUNTIME_FAILSAFE_INFO = 507,
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
} smem_mem_type_t;
#define MSM_SDC1_BASE 0x7800000

19
common/autoboot.c
View file

@ -15,10 +15,12 @@
#include <post.h>
#include <u-boot/sha256.h>
#include <asm/arch-qca-common/qca_common.h>
#include <asm/arch-qca-common/scm.h>
DECLARE_GLOBAL_DATA_PTR;
extern int do_dumpqca_minimal_data(const char *offset);
extern unsigned ipq_runtime_fs_feature_enabled;
#define MAX_DELAY_STOP_STR 32
@ -225,6 +227,9 @@ static int abortboot_normal(int bootdelay)
{
int abort = 0;
unsigned long ts;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned int cookie, ret;
#endif
#ifdef CONFIG_MENUPROMPT
printf(CONFIG_MENUPROMPT);
@ -255,6 +260,20 @@ static int abortboot_normal(int bootdelay)
if (tstc()) { /* we got a key press */
abort = 1; /* don't auto boot */
bootdelay = 0; /* no more delay */
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled) {
cookie = ipq_read_tcsr_boot_misc();
cookie &= ~IPQ_FS_NONHLOS_BIT;
fs_debug("\nFailsafe: %s: Clear NonHLOS bit\n", __func__);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in SCM to clear NonHLOS failsafe bit\n");
}
#endif
# ifdef CONFIG_MENUKEY
menukey = getc();
# else

6
common/board_r.c
View file

@ -64,6 +64,9 @@
#ifdef CONFIG_AVR32
#include <asm/arch/mmu.h>
#endif
#if defined(CONFIG_IPQ_RUNTIME_FAILSAFE)
#include <asm/arch-qca-common/smem.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -951,6 +954,9 @@ init_fnc_t init_sequence_r[] = {
#endif
#if defined(CONFIG_SPARC)
prom_init,
#endif
#if defined(CONFIG_IPQ_RUNTIME_FAILSAFE)
smem_update_bootconfig_to_flash,
#endif
run_main_loop,
};

2
common/cmd_flashwrite.c
View file

@ -33,7 +33,7 @@ extern struct sdhci_host mmc_host;
#define SMEM_PTN_NAME_MAX 16
static int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
uint32_t part_size, uint32_t file_size, char *layout)
{

13
include/configs/ipq6018.h
View file

@ -291,6 +291,19 @@ extern loff_t board_env_size;
#ifdef CONFIG_OF_BOARD_SETUP
#define DLOAD_DISABLE 0x1
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#define CONFIG_HW_WATCHDOG
#define IPQ_FS_NONHLOS_BIT (1 << 9)
#define IPQ_FS_HLOS_BIT (1 << 10)
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE_DEBUG
#define fs_debug(fmt, args...) printf(fmt, ##args);
#else
#define fs_debug(fmt, args...)
#endif
/*
* Below Configs need to be updated after enabling reset_crashdump
* Included now to avoid build failure

17
include/configs/ipq9574.h
View file

@ -285,6 +285,23 @@ extern loff_t board_env_size;
#ifdef CONFIG_OF_BOARD_SETUP
#define DLOAD_DISABLE 0x1
#define CONFIG_IPQ_RUNTIME_FAILSAFE
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#define CONFIG_HW_WATCHDOG
#define IPQ_FS_NONHLOS_BIT (1 << 9)
#define IPQ_FS_HLOS_BIT (1 << 10)
#define IPQ_RUNTIME_FAILSAFE_ENABLED (1 << 0)
#define IPQ_RUNTIME_FS_BOOTCONFIG_UPDATED (1 << 1)
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE_DEBUG
#define fs_debug(fmt, args...) printf(fmt, ##args);
#else
#define fs_debug(fmt, args...)
#endif
/*
* Below Configs need to be updated after enabling reset_crashdump
* Included now to avoid build failure