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ipq5018: update RFA clock to 96MHz

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This changes initialize the CMN block with 96MHz based on
INTERNAL_96MHZ define flag otherwise it will initialize to 48MHz

This changes also enable GMAC0 & GMAC1 AXI clock.

Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ic7f9981394119ea95954ece49d30e36ba4bb2ebd
This commit is contained in:
Vandhiadevan Karunamoorthy 2020-07-15 14:37:08 +05:30 • committed by Gerrit - the friendly Code Review server
parent 7b63c856b6
commit 0930b350c2
3 changed files with 30 additions and 0 deletions
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17
board/qca/arm/ipq5018/ipq5018.c
View file

@ -909,9 +909,19 @@ static void configureRfa_96mhz(void)
static void cmn_clock_init (void)
{
u32 reg_val = 0;
#ifdef INTERNAL_96MHZ
reg_val = readl(CMN_BLK_PLL_SRC_ADDR);
reg_val = ((reg_val & PLL_CTRL_SRC_MASK) |
(CMN_BLK_PLL_SRC_SEL_FROM_REG << 0x8));
writel(reg_val, CMN_BLK_PLL_SRC_ADDR);
reg_val = readl(CMN_BLK_ADDR + 4);
reg_val = (reg_val & PLL_REFCLK_DIV_MASK) | PLL_REFCLK_DIV_2;
writel(reg_val, CMN_BLK_ADDR + 0x4);
#else
reg_val = readl(CMN_BLK_ADDR + 4);
reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK;
writel(reg_val, CMN_BLK_ADDR + 0x4);
#endif
reg_val = readl(CMN_BLK_ADDR);
reg_val = reg_val | 0x40;
writel(reg_val, CMN_BLK_ADDR);
@ -1014,6 +1024,13 @@ static void gcc_clock_enable(void)
reg_val |= 0x1;
writel(reg_val, GCC_SNOC_GMAC1_AHB_CBCR);
reg_val = readl(GCC_SNOC_GMAC0_AXI_CBCR);
reg_val |= 0x1;
writel(reg_val, GCC_SNOC_GMAC0_AXI_CBCR);
reg_val = readl(GCC_SNOC_GMAC1_AXI_CBCR);
reg_val |= 0x1;
writel(reg_val, GCC_SNOC_GMAC1_AXI_CBCR);
}
static void ethernet_clock_enable(void)

7
board/qca/arm/ipq5018/ipq5018.h
View file

@ -52,6 +52,13 @@
#define FREQUENCY_MASK 0xfffffdf0
#define INTERNAL_48MHZ_CLOCK 0x7
#define CMN_BLK_PLL_SRC_ADDR 0x0009B028
#define PLL_CTRL_SRC_MASK 0xfffffcff
#define PLL_REFCLK_DIV_MASK 0xfffffe0f
#define PLL_REFCLK_DIV_2 0x20
#define CMN_BLK_PLL_SRC_SEL_FROM_REG 0x0
#define CMN_BLK_PLL_SRC_SEL_FROM_LOGIC 0x1
#define CMN_BLK_PLL_SRC_SEL_FROM_PCS 0x2
#define TCSR_ETH_LDO_RDY_REG 0x19475C4
#define TCSR_ETH_LDO_RDY_SIZE 0x4
#define ETH_LDO_RDY 0x1

6
include/configs/ipq5018.h
View file

@ -403,4 +403,10 @@ extern loff_t board_env_size;
#define NR_CPUS 2
#endif
/*
* 96 MHz
*/
#define INTERNAL_96MHZ
#endif /* _IPQ5018_H */