mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 08:51:31 +01:00
ipq9574: Clean up eth initialization
This patch does the following: 1) Adds separate function for each init 2) Calls the above individual init functions from eth_init function which is then called in board_eth_init which is called from the core network driver stack during boot up. 3) Adds CMN_BLK init which is needed for NSS Change-Id: I0e5c07bf42f3473b80f524470217879f81c22b1b Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan
Gerrit - the friendly Code Review server
parent
d01203d912
commit
0679e63be7
2 changed files with 235 additions and 52 deletions
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@ -744,97 +744,145 @@ void set_function_select_as_mdc_mdio(void)
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}
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}
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void eth_clock_enable(void)
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void nssnoc_init(void)
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{
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int reg_val, reg_val1, mode, i;
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int node;
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/* Clock init */
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/* Enable required NSSNOC clocks */
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writel(readl(GCC_MEM_NOC_NSSNOC_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_MEM_NOC_NSSNOC_CLK);
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writel(readl(GCC_NSSCFG_CLK) | GCC_CBCR_CLK_ENABLE, GCC_NSSCFG_CLK);
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writel(readl(GCC_NSSNOC_ATB_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_ATB_CLK);
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writel(readl(GCC_NSSNOC_MEM_NOC_1_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_MEM_NOC_1_CLK);
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writel(readl(GCC_NSSNOC_MEMNOC_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_MEMNOC_CLK);
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writel(readl(GCC_NSSNOC_QOSGEN_REF_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_QOSGEN_REF_CLK);
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writel(readl(GCC_NSSNOC_TIMEOUT_REF_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_TIMEOUT_REF_CLK);
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}
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void frequency_init(void)
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{
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unsigned int nss_cc_cfg_addr;
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unsigned int gcc_uniphy_sys_addr;
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unsigned int gcc_pcnoc_addr;
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unsigned int gcc_sysnoc_addr;
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unsigned int reg_val;
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/* Frequency init */
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/* GCC NSS frequency 100M */
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reg_val = readl(0x39B28104 + 4);
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nss_cc_cfg_addr = 0x39B28104;
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reg_val = readl(nss_cc_cfg_addr + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x20f, 0x39B28104 + 4);
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reg_val = readl(0x39B28104);
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writel(reg_val | 0x1, 0x39B28104);
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writel(reg_val | 0x20f, nss_cc_cfg_addr + 4);
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reg_val = readl(nss_cc_cfg_addr);
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writel(reg_val | 0x1, nss_cc_cfg_addr);
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/* GCC CC PPE frequency 353M */
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reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x101, NSS_CC_PPE_FREQUENCY_RCGR + 4);
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reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR);
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writel(reg_val | 0x1, NSS_CC_PPE_FREQUENCY_RCGR);
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/* Uniphy SYS 24M */
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reg_val = readl(0x1817090 + 4);
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gcc_uniphy_sys_addr = 0x1817090;
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reg_val = readl(gcc_uniphy_sys_addr + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x1, 0x1817090 + 4);
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writel(reg_val | 0x1, gcc_uniphy_sys_addr + 4);
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/* Update Config */
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reg_val = readl(0x1817090);
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writel(reg_val | 0x1, 0x1817090);
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reg_val = readl(gcc_uniphy_sys_addr);
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writel(reg_val | 0x1, gcc_uniphy_sys_addr);
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/* PCNOC frequency for Uniphy AHB 100M */
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reg_val = readl(0x1831004 + 4);
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gcc_pcnoc_addr = 0x1831004;
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reg_val = readl(gcc_pcnoc_addr + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x10F, 0x1831004 + 4);
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writel(reg_val | 0x10F, gcc_pcnoc_addr + 4);
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/* Update Config */
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reg_val = readl(0x1831004);
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writel(reg_val | 0x1, 0x1831004);
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reg_val = readl(gcc_pcnoc_addr);
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writel(reg_val | 0x1, gcc_pcnoc_addr);
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/* SYSNOC frequency 343M */
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reg_val = readl(0x182E004 + 4);
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gcc_sysnoc_addr = 0x182E004;
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reg_val = readl(gcc_sysnoc_addr + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x206, 0x182E004 + 4);
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writel(reg_val | 0x206, gcc_sysnoc_addr + 4);
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/* Update Config */
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reg_val = readl(0x182E004);
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writel(reg_val | 0x1, 0x182E004);
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reg_val = readl(gcc_sysnoc_addr);
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writel(reg_val | 0x1, gcc_sysnoc_addr);
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}
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void fixed_nss_csr_clock_init(void)
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{
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unsigned int gcc_nss_csr_addr;
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unsigned int reg_val;
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/* NSS CSR and NSSNOC CSR Clock init */
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reg_val = readl(0x39B281D0);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, 0x39B281D0);
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gcc_nss_csr_addr = 0x39B281D0;
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reg_val = readl(gcc_nss_csr_addr);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr);
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/* NSSNOC CSR */
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reg_val = readl(0x39B281D0 + 4);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, 0x39B281D0 + 4);
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reg_val = readl(gcc_nss_csr_addr + 0x4);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr + 0x4);
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}
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void fixed_sys_clock_init(void)
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{
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unsigned int reg_val;
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/* SYS Clock init */
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/* Enable AHB and SYS clk of CMN */
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reg_val = readl(GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET);
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reg_val = readl(GCC_CMN_BLK_ADDR + GCC_CMN_BLK_SYS_CBCR_OFFSET);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_CMN_BLK_ADDR + GCC_CMN_BLK_SYS_CBCR_OFFSET);
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}
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void fixed_uniphy_clock_init(void)
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{
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int i;
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unsigned int reg_val;
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/* Uniphy AHB AND SYS CBCR init */
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for (i = 0; i < 3; i++) {
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reg_val = readl(GCC_UNIPHY_SYS_ADDR + i*0x10);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_UNIPHY_SYS_ADDR + i*0x10);
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reg_val = readl((GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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(GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10);
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}
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}
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void port_mac_clock_init(void)
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{
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int i;
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unsigned int reg_val;
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/* Port Mac Clock init */
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for (i = 0; i < 6; i++) {
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reg_val = readl(GCC_PORT_MAC_ADDR + i*0x4);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_PORT_MAC_ADDR + i*0x4);
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}
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}
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void cfg_clock_init(void)
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{
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int i;
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unsigned int reg_val;
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/* CFG Clock init */
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for (i = 0; i < 8; i++) {
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@ -844,42 +892,113 @@ void eth_clock_enable(void)
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}
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reg_val = readl(NSS_CC_PPE_SWITCH_BTQ_ADDR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_PPE_SWITCH_BTQ_ADDR);
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}
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void mdio_clock_init(void)
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{
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unsigned int reg_val;
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/* MDIO Clock init */
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reg_val = readl(GCC_MDIO_AHB_CBCR_ADDR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MDIO_AHB_CBCR_ADDR);
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}
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void noc_clock_init(void)
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{
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unsigned int reg_val;
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/* NOC Clock init */
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reg_val = readl(GCC_NSSNOC_SNOC_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_NSSNOC_SNOC_CBCR);
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reg_val = readl(GCC_NSSNOC_SNOC_1_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_NSSNOC_SNOC_1_CBCR);
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reg_val = readl(GCC_MEM_NOC_SNOC_AXI_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MEM_NOC_SNOC_AXI_CBCR);
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reg_val = readl(GCC_IMEM_AXI_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_IMEM_AXI_CBCR);
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}
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/* Enable mac clock */
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for (i = 0; i < 6; i++) {
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reg_val = readl(NSS_CC_PORT1_RX_CBCR + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_PORT1_RX_CBCR + i*0x8);
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reg_val = readl(NSS_CC_PORT1_RX_CBCR + 0x4 + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_PORT1_RX_CBCR + 0x4 + i*0x8);
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void fixed_clock_init(void)
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{
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frequency_init();
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fixed_nss_csr_clock_init();
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fixed_sys_clock_init();
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fixed_uniphy_clock_init();
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port_mac_clock_init();
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cfg_clock_init();
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mdio_clock_init();
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noc_clock_init();
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}
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void uniphy_clock_enable(enum uniphy_clk_type clk_type, bool enable)
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{
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unsigned int reg_val, i;
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i = clk_type;
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if (clk_type <= NSS_PORT6_TX_CLK_E) {
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reg_val = readl(NSS_CC_PORT1_RX_CBCR + i*0x4);
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if (enable)
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reg_val |= GCC_CBCR_CLK_ENABLE;
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else
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reg_val &= ~GCC_CBCR_CLK_ENABLE;
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writel(reg_val, (NSS_CC_PORT1_RX_CBCR + i*0x4));
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} else {
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if (i >= UNIPHY1_PORT5_RX_CLK_E) {
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i = i - 2;
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}
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + (i - 12)*0x4);
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if (enable)
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reg_val |= GCC_CBCR_CLK_ENABLE;
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else
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reg_val &= ~GCC_CBCR_CLK_ENABLE;
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writel(reg_val, (NSS_CC_UNIPHY_PORT1_RX_CBCR + (i - 12)*0x4));
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}
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}
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/* Enable Uniphy clock */
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for (i = 0; i < 6; i++) {
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_UNIPHY_PORT1_RX_CBCR + i*0x8);
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + i*0x8);
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}
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writel(0x1, NSS_CC_PORT5_RX_CMD_RCGR);
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writel(0x2, NSS_CC_PORT5_RX_CMD_RCGR);
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writel(0x1, NSS_CC_PORT5_TX_CMD_RCGR);
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writel(0x2, NSS_CC_PORT5_TX_CMD_RCGR);
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void uniphy_clk_init(void)
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{
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int i;
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/* Uniphy clock enable */
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for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++)
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uniphy_clock_enable(i, true);
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}
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void cmnblk_init(void)
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{
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uint32_t gcc_pll_base, reg_val;
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gcc_pll_base = CMN_BLK_ADDR;
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reg_val = readl(gcc_pll_base + 4);
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reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK;
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writel(reg_val, gcc_pll_base + 0x4);
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reg_val = readl(gcc_pll_base);
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reg_val = reg_val | 0x40;
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writel(reg_val, gcc_pll_base);
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mdelay(1);
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reg_val = reg_val & (~0x40);
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writel(reg_val, gcc_pll_base);
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mdelay(1);
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writel(0xbf, gcc_pll_base);
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mdelay(1);
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writel(0xff, gcc_pll_base);
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mdelay(1);
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}
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void uniphy_port5_clock_source_set(void)
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{
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int reg_val, reg_val1, node, mode;
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/* Uniphy Port5 clock source set */
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reg_val = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x64);
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reg_val1 = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x70);
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@ -893,30 +1012,33 @@ void eth_clock_enable(void)
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printf("\nError: switch_mac_mode1 not specified in dts");
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return;
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}
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if (mode == 0xFF) { /* PORT_WRAPPER_MAX */
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if (mode == PORT_WRAPPER_MAX) { /* PORT_WRAPPER_MAX */
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reg_val |= 0x200;
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reg_val1 |= 0x300;
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} else {
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reg_val |= 0x400;
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reg_val |= 0x500;
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reg_val1 |= 0x500;
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}
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writel(reg_val, NSS_CC_PORT_SPEED_DIVIDER + 0x64);
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writel(0x1, NSS_CC_PORT_SPEED_DIVIDER + 0x60);
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writel(reg_val1, NSS_CC_PORT_SPEED_DIVIDER + 0x70);
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writel(0x1, NSS_CC_PORT_SPEED_DIVIDER + 0x6c);
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}
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void nss_ppe_reset(void)
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{
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unsigned int reg_val;
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/* PPE Clock init and NSS PPE Assert/De-assert */
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reg_val = readl(NSS_CC_PPE_RESET_ADDR);
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writel(reg_val | 0x1e0000, NSS_CC_PPE_RESET_ADDR);
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mdelay(500);
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writel(reg_val & (~0x1e0000), NSS_CC_PPE_RESET_ADDR);
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mdelay(100);
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}
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/* Set function select as MDI */
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set_function_select_as_mdc_mdio();
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/* Bring PHY out of RESET */
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void bring_phy_out_of_reset(void)
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{
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qca807x_phy_reset_init();
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aquantia_phy_reset_init();
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qca808x_phy_reset_init();
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@ -926,6 +1048,31 @@ void eth_clock_enable(void)
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qca808x_phy_reset_init_done();
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mdelay(500);
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}
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void eth_clock_init(void)
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{
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nssnoc_init();
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fixed_clock_init();
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uniphy_clk_init();
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cmnblk_init();
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uniphy_port5_clock_source_set();
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}
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void ipq9574_eth_initialize(void)
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{
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eth_clock_init();
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nss_ppe_reset();
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set_function_select_as_mdc_mdio();
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bring_phy_out_of_reset();
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}
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#endif
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#ifdef CONFIG_IPQ9574_EDMA
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@ -934,7 +1081,7 @@ int board_eth_init(bd_t *bis)
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int ret = 0;
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#ifndef CONFIG_IPQ9574_RUMI
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eth_clock_enable();
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ipq9574_eth_initialize();
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#endif
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ret = ipq9574_edma_init(NULL);
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@ -18,6 +18,11 @@
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#include <asm/u-boot.h>
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#include <asm/arch-qca-common/qca_common.h>
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#define CMN_BLK_ADDR 0x0009B780
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#define FREQUENCY_MASK 0xfffffdf0
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#define INTERNAL_48MHZ_CLOCK 0x7
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#define PORT_WRAPPER_MAX 0xFF
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/*
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* EDMA HW ASSERT and DEASSERT values
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*/
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@ -213,6 +218,37 @@
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#define USB3_PHY_SW_RESET 0x800
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#define NOC_HANDSHAKE_FSM_EN (1 << 15)
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enum uniphy_clk_type {
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NSS_PORT1_RX_CLK_E = 0,
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NSS_PORT1_TX_CLK_E,
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NSS_PORT2_RX_CLK_E,
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NSS_PORT2_TX_CLK_E,
|
||||
NSS_PORT3_RX_CLK_E,
|
||||
NSS_PORT3_TX_CLK_E,
|
||||
NSS_PORT4_RX_CLK_E,
|
||||
NSS_PORT4_TX_CLK_E,
|
||||
NSS_PORT5_RX_CLK_E,
|
||||
NSS_PORT5_TX_CLK_E,
|
||||
NSS_PORT6_RX_CLK_E,
|
||||
NSS_PORT6_TX_CLK_E,
|
||||
UNIPHY0_PORT1_RX_CLK_E,
|
||||
UNIPHY0_PORT1_TX_CLK_E,
|
||||
UNIPHY0_PORT2_RX_CLK_E,
|
||||
UNIPHY0_PORT2_TX_CLK_E,
|
||||
UNIPHY0_PORT3_RX_CLK_E,
|
||||
UNIPHY0_PORT3_TX_CLK_E,
|
||||
UNIPHY0_PORT4_RX_CLK_E,
|
||||
UNIPHY0_PORT4_TX_CLK_E,
|
||||
UNIPHY0_PORT5_RX_CLK_E,
|
||||
UNIPHY0_PORT5_TX_CLK_E,
|
||||
UNIPHY1_PORT5_RX_CLK_E,
|
||||
UNIPHY1_PORT5_TX_CLK_E,
|
||||
UNIPHY2_PORT6_RX_CLK_E,
|
||||
UNIPHY2_PORT6_TX_CLK_E,
|
||||
PORT5_RX_SRC_E,
|
||||
PORT5_TX_SRC_E,
|
||||
UNIPHYT_CLK_MAX,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI_IPQ
|
||||
void board_pci_init(int id);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue