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Revert "ipq9574: Power collapse UBI32 Cores"

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This reverts commit 5dfb1b4291.

Change-Id: I61579a05e35a29e3104179b5e917344f4ee375bb
Signed-off-by: Gaurao Chaudhari <quic_gaurchau@quicinc.com>
This commit is contained in:
Gaurao Chaudhari 2022-04-01 11:12:11 -07:00
parent 252874cd42
commit 02dafe6a94
8 changed files with 0 additions and 37 deletions
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2
board/qca/arm/common/board_init.c
View file

@ -408,8 +408,6 @@ int board_late_init(void)
#ifdef CONFIG_FLASH_PROTECT
board_flash_protect();
#endif
ubi_power_collapse();
set_ethmac_addr();
/*

1
board/qca/arm/ipq40xx/ipq40xx.h
View file

@ -71,7 +71,6 @@ __weak void aquantia_phy_reset_init_done(void) {}
__weak void aquantia_phy_reset_init(void) {}
__weak void qgic_init(void) {}
__weak void handle_noc_err(void) {}
__weak void ubi_power_collapse(void) {}
__weak int ipq_get_tz_version(char *version_name, int buf_size)
{
return 1;

1
board/qca/arm/ipq5018/ipq5018.h
View file

@ -553,7 +553,6 @@ __weak void aquantia_phy_reset_init(void) {}
__weak void qgic_init(void) {}
__weak void handle_noc_err(void) {}
__weak void board_pcie_clock_init(int id) {}
__weak void ubi_power_collapse(void) {}
struct smem_ram_ptable {
#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8

1
board/qca/arm/ipq6018/ipq6018.h
View file

@ -390,6 +390,5 @@ __weak void board_pcie_clock_init(int id) {}
__weak void qgic_init(void) {}
__weak void handle_noc_err(void) {}
__weak void ubi_power_collapse(void) {}
#endif /* _IPQ6018_CDP_H_ */

1
board/qca/arm/ipq806x/ipq806x.h
View file

@ -156,7 +156,6 @@ __weak void aquantia_phy_reset_init_done(void) {}
__weak void aquantia_phy_reset_init(void) {}
__weak void qgic_init(void) {}
__weak void handle_noc_err(void) {}
__weak void ubi_power_collapse(void) {}
struct smem_ram_ptn {
char name[16];

1
board/qca/arm/ipq807x/ipq807x.h
View file

@ -315,7 +315,6 @@ void qgic_init(void);
void handle_noc_err(void);
void ipq_fdt_fixup_socinfo(void *blob);
int ipq_board_usb_init(void);
__weak void ubi_power_collapse(void) {}
unsigned smem_read_alloc_entry(smem_mem_type_t type, void *buf, int len);
__weak int ipq_get_tz_version(char *version_name, int buf_size)
{

20
board/qca/arm/ipq9574/ipq9574.c
View file

@ -1216,26 +1216,6 @@ int board_eth_init(bd_t *bis)
}
#endif
void ubi_power_collapse(void)
{
/* Enable NSS CSR clocks to access the UBI Power collapse registers */
writel(0x20f, NSS_CC_CFG_CFG_RCGR);
writel(0x1, NSS_CC_CFG_CMD_RCGR);
writel(GCC_CBCR_CLK_ENABLE, NSS_CC_NSS_CSR_CBCR);
writel(GCC_CBCR_CLK_ENABLE, NSS_CC_NSSNOC_NSS_CSR_CBCR);
/* Power collapsing the 4 UBI32 Cores as it is not used in IPQ9574 */
writel(readl(UBI_C0_GDS_CTRL_REQ) | UBI32_CORE_GDS_COLLAPSE_EN_SW,
UBI_C0_GDS_CTRL_REQ);
writel(readl(UBI_C1_GDS_CTRL_REQ) | UBI32_CORE_GDS_COLLAPSE_EN_SW,
UBI_C1_GDS_CTRL_REQ);
writel(readl(UBI_C2_GDS_CTRL_REQ) | UBI32_CORE_GDS_COLLAPSE_EN_SW,
UBI_C2_GDS_CTRL_REQ);
writel(readl(UBI_C3_GDS_CTRL_REQ) | UBI32_CORE_GDS_COLLAPSE_EN_SW,
UBI_C3_GDS_CTRL_REQ);
}
unsigned long timer_read_counter(void)
{
return 0;

10
board/qca/arm/ipq9574/ipq9574.h
View file

@ -82,15 +82,6 @@
#define GCC_PORT6_ARES 0x3
#define NSS_CC_PORT_SPEED_DIVIDER 0x39B28110
#define NSS_CC_PPE_FREQUENCY_RCGR 0x39B28204
#define NSS_CC_CFG_CMD_RCGR 0x39B28104
#define NSS_CC_CFG_CFG_RCGR 0x39B28108
#define NSS_CC_NSS_CSR_CBCR 0x39B281D0
#define NSS_CC_NSSNOC_NSS_CSR_CBCR 0x39B281D4
#define UBI_C0_GDS_CTRL_REQ 0x39D00020
#define UBI_C1_GDS_CTRL_REQ 0x39D00024
#define UBI_C2_GDS_CTRL_REQ 0x39D00028
#define UBI_C3_GDS_CTRL_REQ 0x39D0002C
#define UBI32_CORE_GDS_COLLAPSE_EN_SW 0x1 << 28
#define GPIO_DRV_2_MA 0x0 << 6
#define GPIO_DRV_4_MA 0x1 << 6
@ -391,7 +382,6 @@ typedef enum {
#define MSM_SDC1_BASE 0x7800000
#define MSM_SDC1_SDHCI_BASE 0x7804000
void ubi_power_collapse(void);
__weak void qgic_init(void) {}
__weak void handle_noc_err(void) {}
extern const char *rsvd_node;