From 0206407f5fb6b9bcd2ee89cf78158a34679a69c4 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Fri, 6 Sep 2019 15:56:52 +0530 Subject: [PATCH] ipq807x: added support for HK10 external reference clk select. By default UNIPHY PLL takes 48MHz, now this need to take 50M from external oscilator input pin for HK10. So need to change the PLL ref sel. Affected only for HK10. Tested on Reworked HK01 board with 50MHz oscillator connected to USGMII_OSCILL_50M pin Change-Id: Ie90fdbbfbfc700a30d9ada895baa1a170db25888 Signed-off-by: Tushar Nimkar --- arch/arm/dts/ipq807x-hk10.dts | 1 + board/qca/arm/ipq807x/ipq807x.c | 18 +++++++++++++++++- board/qca/arm/ipq807x/ipq807x.h | 10 ++++++++++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/ipq807x-hk10.dts b/arch/arm/dts/ipq807x-hk10.dts index d8800de1d6..aa9947beb3 100644 --- a/arch/arm/dts/ipq807x-hk10.dts +++ b/arch/arm/dts/ipq807x-hk10.dts @@ -31,6 +31,7 @@ switch_mac_mode2 = <0x6>; napa_gpio = <25 44>; napa_gpio_cnt = <2>; + uniphy_ext_ref_clk; port_phyinfo { port@0 { phy_address = <0>; diff --git a/board/qca/arm/ipq807x/ipq807x.c b/board/qca/arm/ipq807x/ipq807x.c index fa2dce3228..b6ac0a2f23 100644 --- a/board/qca/arm/ipq807x/ipq807x.c +++ b/board/qca/arm/ipq807x/ipq807x.c @@ -424,7 +424,20 @@ void aquantia_phy_reset_init_done(void) gpio_set_value(aquantia_gpio, 0x1); } } - +void check_uniphy_ext_ref_clk(void) +{ + int node; + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) { + if(fdtdec_get_bool(gd->fdt_blob, node, "uniphy_ext_ref_clk")){ + printf("External ref clk setting found... \n"); + writel(PLL_REF_CLKSEL_50M, PLL_REFERENCE_CLOCK); /*0x8218 - 50M 0x8017 - 48M(default)*/ + writel(ANA_EN_SW_RSTN_DIS, PLL_POWER_ON_AND_RESET); /*give reset*/ + mdelay(1); + writel(ANA_EN_SW_RSTN_EN, PLL_POWER_ON_AND_RESET); + } + } +} void eth_clock_enable(void) { int tlmm_base = 0x1025000; @@ -482,6 +495,9 @@ void eth_clock_enable(void) * these clk init will be moved to sbl later */ + /*this is for ext oscillator clk for ref clk-*/ + check_uniphy_ext_ref_clk(); + /* bring phy out of reset */ writel(7, tlmm_base + 0x1f000); writel(7, tlmm_base + 0x20000); diff --git a/board/qca/arm/ipq807x/ipq807x.h b/board/qca/arm/ipq807x/ipq807x.h index c161dd48f3..dd128e7c59 100644 --- a/board/qca/arm/ipq807x/ipq807x.h +++ b/board/qca/arm/ipq807x/ipq807x.h @@ -232,6 +232,16 @@ #define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3) #define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4) +/*CMN BLOCK REG*/ +#define PLL_REFERENCE_CLOCK 0x0009B784 +#define PLL_POWER_ON_AND_RESET 0x0009B780 + +/*0x8218 - 50M 0x8017 - 48M(default)*/ +#define PLL_REF_CLKSEL_50M 0x8218 + +#define ANA_EN_SW_RSTN_DIS 0xBF +#define ANA_EN_SW_RSTN_EN 0xFF + unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int, unsigned int, unsigned int);