diff --git a/board/qca/arm/devsoc/devsoc.c b/board/qca/arm/devsoc/devsoc.c
index 7293cbdada..bd3c3d35a3 100644
--- a/board/qca/arm/devsoc/devsoc.c
+++ b/board/qca/arm/devsoc/devsoc.c
@@ -143,12 +143,22 @@ void board_nand_init(void)
 
 void enable_caches(void)
 {
+	qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
+	smem_get_boot_flash(&sfi->flash_type,
+		&sfi->flash_index,
+		&sfi->flash_chip_select,
+		&sfi->flash_block_size,
+		&sfi->flash_density);
 	icache_enable();
+	/*Skips dcache_enable during JTAG recovery */
+	if (sfi->flash_type)
+		dcache_enable();
 }
 
 void disable_caches(void)
 {
 	icache_disable();
+	dcache_disable();
 }
 
 unsigned long timer_read_counter(void)
diff --git a/include/configs/devsoc.h b/include/configs/devsoc.h
index 608d2f0ab2..5ac9e803a1 100644
--- a/include/configs/devsoc.h
+++ b/include/configs/devsoc.h
@@ -24,7 +24,6 @@
 #undef	CONFIG_QCA_DISABLE_SCM
 #define CONFIG_SPI_FLASH_CYPRESS
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CACHELINE_SIZE		64
 #define CONFIG_IPQ_NO_RELOC
 
 #define CONFIG_SYS_VSNPRINTF
@@ -213,6 +212,7 @@ extern loff_t board_env_size;
 * Cache flush and invalidation based on L1 cache, so the cache line
 * size is configured to 64 */
 #define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_CMD_CACHE
 
 /*
 * SPI Flash Configs