mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2025-12-10 07:44:53 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge "arm: dts: Add MI04.3 (RDP483) dts support"

Browse source
This commit is contained in:
Linux Build Service Account 2023-11-09 01:22:14 -08:00 • committed by Gerrit - the friendly Code Review server
commit 0133affe21
3 changed files with 229 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/Makefile
View file

@ -101,12 +101,14 @@ dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-emulation.dtb \
ipq5332-mi01.9.dtb \
ipq5332-mi03.1.dtb \
ipq5332-mi04.1.dtb \
ipq5332-mi04.3.dtb \
ipq5332-db-mi01.1.dtb \
ipq5332-db-mi02.1.dtb \
ipq5332-db-mi03.1.dtb
else
ifneq ($(CONFIG_IPQ_TINY_SPI_NOR),y)
dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-mi01.3.dtb \
ipq5332-mi04.3.dtb \
ipq5332-mi04.1.dtb \
ipq5332-db-mi02.1.dtb
else

226
arch/arm/dts/ipq5332-mi04.3.dts Normal file
View file

@ -0,0 +1,226 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "ipq5332-soc.dtsi"
/ {
machid = <0x8060107>;
config_name = "config@mi04.3", "config@rdp483", "config-rdp483";
aliases {
console = "/serial@78AF000";
nand = "/nand-controller@79B0000";
usb0 = "/xhci@8a00000";
i2c0 = "/i2c@78B6000";
pci1 = "/pci@18000000";
pci2 = "/pci@10000000";
};
serial@78AF000 {
status = "ok";
serial_gpio {
blsp0_uart_rx {
gpio = <18>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
blsp0_uart_tx {
gpio = <19>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
};
};
spi {
spi_gpio {
blsp0_spi_clk {
gpio = <14>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_mosi {
gpio = <15>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_miso {
gpio = <16>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_cs {
gpio = <17>;
func = <1>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
i2c@78B6000 {
i2c_gpio {
gpio1 {
gpio = <29>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
gpio2 {
gpio = <30>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
};
};
nand: nand-controller@79B0000 {
nand_gpio {
qspi_dat3 {
gpio = <8>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat2 {
gpio = <9>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat1 {
gpio = <10>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat0 {
gpio = <11>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_cs_n {
gpio = <12>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
qspi_clk {
gpio = <13>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
};
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <47>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci2: pci@10000000 {
status = "ok";
perst_gpio = <44>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <44>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
qca8084_switch_enable = <1>;
qca8084_bypass_enable = <1>;
port_phyinfo {
port@0 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <0>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
port@1 {
phy_address = <4>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_SGMII0_RGMII4>;
};
};
qca8084_swt_info {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_MAX>;
port@0 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
port@1 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@4 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
port@5 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
};
};
};

1
arch/arm/include/asm/mach-types.h
View file

@ -1181,6 +1181,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_IPQ5332_AP_MI01_3_C2 0x8060102
#define MACH_TYPE_IPQ5332_AP_MI04_1 0x8060004
#define MACH_TYPE_IPQ5332_AP_MI04_1_C2 0x8060007
#define MACH_TYPE_IPQ5332_AP_MI04_3 0x8060107
#define MACH_TYPE_IPQ5332_AP_MI01_12 0x8060202
#define MACH_TYPE_IPQ5332_AP_MI01_14 0x8060302