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drivers: net: ipq9574: uniphy clock init update

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Uniphy clk init and deinit creates additional delay in UBoot.
Falling back to Uniphy clk init during boot up and not doing
de-init during speed changes.

Change-Id: I10fb86e4b616f46c2a0c3066308e7c6a6325cf44
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-08-19 11:08:04 +05:30 • committed by Gerrit - the friendly Code Review server
parent 73dec84a77
commit 00277b03ad
3 changed files with 3 additions and 21 deletions
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14
board/qca/arm/ipq9574/ipq9574.c
View file

@ -966,20 +966,12 @@ void uniphy_clock_enable(enum uniphy_clk_type clk_type, bool enable)
}
}
void uniphy_clk_init(void)
void uniphy_clk_init(bool enable)
{
int i;
/* Uniphy clock enable */
for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++)
uniphy_clock_enable(i, true);
}
void uniphy_clk_deinit(void)
{
int i;
/* Uniphy clock enable */
for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++)
uniphy_clock_enable(i, false);
uniphy_clock_enable(i, enable);
}
void cmnblk_init(void)
@ -1063,7 +1055,7 @@ void eth_clock_init(void)
fixed_clock_init();
uniphy_clk_init();
uniphy_clk_init(true);
cmnblk_init();

5
drivers/net/ipq9574/ipq9574_edma.c
View file

@ -49,7 +49,6 @@ uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0};
int sgmii_mode[2] = {0};
extern void uniphy_clk_deinit(void);
extern int ipq_sw_mdio_init(const char *);
extern int ipq_mdio_read(int mii_id, int regnum, ushort *data);
extern void ipq9574_qca8075_phy_map_ops(struct phy_ops **ops);
@ -1191,10 +1190,6 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
}
}
uniphy_clk_deinit();
mdelay(150);
ipq9574_speed_clock_set(i, clk);
ipq9574_port_mac_clock_reset(i);

5
drivers/net/ipq9574/ipq9574_ppe.c
View file

@ -32,7 +32,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define pr_info(fmt, args...) printf(fmt, ##args);
extern void uniphy_clk_init(void);
extern void uniphy_port5_clock_source_set(void);
/*
@ -460,8 +459,6 @@ void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex,
ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
ppe_xgmac_speed_set(port, speed);
uniphy_clk_init();
mdelay(150);
ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
ppe_uniphy_usxgmii_port_reset(uniphy_index);
ppe_port_bridge_txmac_set(port + 1, status);
@ -474,8 +471,6 @@ void ipq9574_pqsgmii_speed_set(int port, int speed, int status)
{
ppe_port_bridge_txmac_set(port + 1, status);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed);
uniphy_clk_init();
mdelay(150);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73);
ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5);
}