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133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
/*
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* Copyright (C) 2009-2016 Realtek Semiconductor Corp.
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* All Rights Reserved.
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*
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* This program is the proprietary software of Realtek Semiconductor
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* Corporation and/or its licensors, and only be used, duplicated,
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* modified or distributed under the authorized license from Realtek.
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*
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* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
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* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
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*
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* $Revision: 73171 $
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* $Date: 2016-11-09 17:03:46 +0800 (Wed, 09 Nov 2016) $
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*
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* Purpose : Definition of OSAL test APIs in the SDK
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*
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* Feature : OSAL test APIs
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*
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*/
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/*
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* Include Files
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*/
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#include <osal/osal_test_case.h>
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#include <private/drv/swcore/swcore.h>
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#include <hwp/hw_profile.h>
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#define VERI_ISR_TIMES (8)
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static volatile int global_run_times = 0;
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static volatile int even_fail = 0;
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uint32 g_family_id, g_chip_id, g_chip_rev_id;
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osal_isrret_t isr_handler(uint32 unit, void *data){
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/* How much interrupt occurd */
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global_run_times++;
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SHOWMESSAGE("Hello: %d\n", global_run_times);
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/* Clear TC1 pending flag */
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if(HWP_8390_50_FAMILY(unit))
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REG32(RTL8390MP_TC1INT) |= RTL8390MP_TCIP;
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if(HWP_8380_30_FAMILY(unit))
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REG32(RTL8380MP_TC1INT) |= RTL8380MP_TCIP;
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return RT_ERR_OK;
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}
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void remove_interrupt_handler(uint32 unit)
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{
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/* unregister isr */
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if(HWP_8390_50_FAMILY(unit))
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{
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REG32(RTL8390MP_TC1CTL) &= ~(RTL8390MP_TCEN | RTL8390MP_TCMODE_TIMER);
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REG32(RTL8390MP_TC1INT) &= ~RTL8390MP_TCIE;
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}
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if(HWP_8380_30_FAMILY(unit))
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{
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REG32(RTL8380MP_TC1CTL) &= ~(RTL8380MP_TCEN | RTL8380MP_TCMODE_TIMER);
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REG32(RTL8380MP_TC1INT) &= ~RTL8380MP_TCIE;
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}
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REG32(GIMR) &= ~(0x10000000); /* TC1IE */
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osal_isr_unregister(RTK_DEV_TC1);
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SHOWMESSAGE("Unregister TC1 ISR\n");
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}
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int32 osal_isr_test(uint32 caseNo, uint32 unit)
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{
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char name[32];
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volatile int checking;
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RT_LOG(LOG_FUNC_ENTER, MOD_UNITTEST, "[%s] Running ISR test cases", __FUNCTION__);
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global_run_times = 0;
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even_fail = 0;
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if(HWP_8390_50_FAMILY(unit))
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{
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/* Set trigger period */
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REG32(RTL8390MP_TC1CTL) = 0; /* disable timer before setting CDBR */
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REG32(RTL8390MP_TC1DATA) = (20000);
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REG32(RTL8390MP_TC1CTL) = RTL8390MP_TCEN | RTL8390MP_TCMODE_TIMER | DIVISOR_RTL8390 ;
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REG32(RTL8390MP_TC1INT) = RTL8390MP_TCIE;
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}
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if(HWP_8380_30_FAMILY(unit))
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{
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/* Set trigger period */
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REG32(RTL8380MP_TC1CTL) = 0; /* disable timer before setting CDBR */
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REG32(RTL8380MP_TC1DATA) = (20000);
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REG32(RTL8380MP_TC1CTL) = RTL8380MP_TCEN | RTL8380MP_TCMODE_TIMER | DIVISOR ;
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REG32(RTL8380MP_TC1INT) = RTL8380MP_TCIE;
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}
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/* Install ISR */
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osal_isr_register(RTK_DEV_TC1, isr_handler, name);
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REG32(GIMR) |= 0x10000000; //TC1IE
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/* Wait 5 secs for increasing global_run_times */
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osal_time_sleep(5);
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if( 0==global_run_times ){
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even_fail++;
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goto isr_fail;
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}
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while( VERI_ISR_TIMES>global_run_times );
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/* Un-install ISR */
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remove_interrupt_handler(unit);
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checking = global_run_times;
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/* The ISR handler is unregisted, and the
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* global_run_times must be equal to VERI_ISR_TIMES
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*/
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osal_time_sleep(5);
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if( checking != global_run_times ){
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even_fail++;
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}
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isr_fail:
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if( 0==even_fail )
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{
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osal_printf("[OSAL ISR Test Pass]\n");
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return RT_ERR_OK;
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}
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else
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{
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osal_printf("[OSAL ISR Test Fail]\n");
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return RT_ERR_FAILED;
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}
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}
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