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106 lines
4 KiB
C
Executable file
106 lines
4 KiB
C
Executable file
/*
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* Copyright (C) 2009-2016 Realtek Semiconductor Corp.
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* All Rights Reserved.
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*
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* This program is the proprietary software of Realtek Semiconductor
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* Corporation and/or its licensors, and only be used, duplicated,
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* modified or distributed under the authorized license from Realtek.
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*
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* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
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* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
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*
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* $Revision$
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* $Date$
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*
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* Purpose : PHY symbol and data type definition in the SDK.
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*
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* Feature : PHY symbol and data type definition
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*
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*/
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#ifndef __HAL_PHY_PHYDEF_H__
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#define __HAL_PHY_PHYDEF_H__
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#include "ptp.h"
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/* definition phy driver structure */
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typedef struct rt_phydrv_s
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{
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rtk_int32 phydrv_index;
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ret_t (*fPhydrv_init)(rtk_port_t);
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ret_t (*fPhydrv_ptpRefTime_get)(rtk_time_timeStamp_t *);
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ret_t (*fPhydrv_ptpRefTime_set)(rtk_time_timeStamp_t);
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ret_t (*fPhydrv_PtpbypassptpEn_get)(rtk_port_t , rtk_enable_t *);
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ret_t (*fPhydrv_PtpbypassptpEn_set)(rtk_port_t , rtk_enable_t );
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ret_t (*fPhydrv_PtpEnable_get)(rtk_port_t ,rtk_ptp_header_t, rtk_enable_t *);
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ret_t (*fPhydrv_PtpEnable_set)(rtk_port_t ,rtk_ptp_header_t,rtk_enable_t );
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ret_t (*fPhydrv_RefTimeAdjust_set)( rtk_uint32 , rtk_time_timeStamp_t );
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ret_t (*fPhydrv_RefTimeEnable_get)( rtk_enable_t *);
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ret_t (*fPhydrv_RefTimeEnable_set)( rtk_enable_t );
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ret_t (*fPhydrv_PtpVlanTpid_get)( rtk_vlanType_t , rtk_uint32 , rtk_uint32 *);
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ret_t (*fPhydrv_PtpVlanTpid_set)(rtk_vlanType_t , rtk_uint32 , rtk_uint32 );
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ret_t (*fPhydrv_PtpOper_get)(rtk_time_operCfg_t *);
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ret_t (*fPhydrv_PtpOper_set)( rtk_time_operCfg_t );
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ret_t (*fPhydrv_PtpLatchTime_get)( rtk_time_timeStamp_t *);
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ret_t (*fPhydrv_PtpRefTimeFreqCfg_get)(rtk_uint32 *, rtk_uint32 *);
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ret_t (*fPhydrv_PtpRefTimeFreqCfg_set)(rtk_uint32, rtk_enable_t);
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ret_t (*fPhydrv_PtpTxInterruptStatus_get)( rtk_uint32 *);
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ret_t (*fPhydrv_PtpTxTimestampFifo_get)(rtk_time_txTimeEntry_t *);
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ret_t (*fPhydrv_Ptp1PPSOutput_get)(rtk_uint32 *, rtk_enable_t *);
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ret_t (*fPhydrv_Ptp1PPSOutput_set)( rtk_uint32, rtk_enable_t);
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ret_t (*fPhydrv_PtpClockOutput_get)( rtk_time_clkOutput_t*);
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ret_t (*fPhydrv_PtpClockOutput_set)( rtk_time_clkOutput_t );
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ret_t (*fPhydrv_PtpToddelay_get)( rtk_uint32 *);
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ret_t (*fPhydrv_PtpToddelay_set)( rtk_uint32 );
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ret_t (*fPhydrv_PtpOutputSigSel_get)( rtk_time_outSigSel_t *);
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ret_t (*fPhydrv_PtpOutputSigSel_set)( rtk_time_outSigSel_t);
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ret_t (*fPhydrv_PtpPortctrl_get)( rtk_port_t, rtk_ptp_port_ctrl_t*);
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ret_t (*fPhydrv_PtpPortctrl_set)(rtk_port_t, rtk_ptp_port_ctrl_t);
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} rt_phydrv_t;
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typedef ret_t (*phy_ident_f)( rtk_uint32 model_id, rtk_uint32 rev_id);
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//typedef void (*fPhydrv_mapperInit_f)(rt_phydrv_t* pPhydrv);
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typedef rt_phydrv_t *(*fPhydrv_mapperInit_f)(void);
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/* Definition family ID */
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#define RTL8371_FAMILY_ID (0x83710000)
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#define RTK_PHYINFO_FLAG_NONE (0x0)
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#define PHY_MODEL_ID_NULL (0x0)
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typedef enum phy_type_e {
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RTK_PHYTYPE_NONE = 0, /* no phy connected */
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RTK_PHYTYPE_RTL8224,
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RTK_PHYTYPE_RTL8221B,
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RTK_PHYTYPE_RTL8218E,
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RTK_PHYTYPE_SERDES,
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RTK_PHYTYPE_UNKNOWN, /* phy connected, but unknown type */
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RTK_PHYTYPE_INVALID, /* somehting wrong in hardware profile */
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RTK_PHYTYPE_END,
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} phy_type_t_rtl8372;
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/* enum for supported phy driver */
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typedef enum rt_supported_phydrv_e
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{
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RT_PHYDRV_RTL8224,
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RT_PHYDRV_END
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} rt_supported_phydrv_t;
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typedef struct rt_phyInfo_s
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{
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rtk_uint32 phy_num; /* PHY number in the chip, like 8218 is 8, 8224C is 4 */
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rtk_uint32 eth_type; /* PHY speed*/
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} rt_phyInfo_t;
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/* definition phy control structure */
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typedef struct rt_phyctrl_s
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{
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phy_ident_f chk_func;
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rtk_uint32 phy_model_id;
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rtk_uint32 phy_rev_id;
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phy_type_t_rtl8372 phyType;
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rt_phydrv_t *pPhydrv;
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fPhydrv_mapperInit_f mapperInit_func;
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rtk_uint32 drv_rev_id;
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rt_phyInfo_t *pPhyInfo;
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} rt_phyctrl_t;
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#endif
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