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203 lines
6.3 KiB
C
203 lines
6.3 KiB
C
#ifndef _RTL8261_PHY_H_
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#define _RTL8261_PHY_H_
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#define BIT_0 0x00000001U
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#define BIT_1 0x00000002U
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#define BIT_2 0x00000004U
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#define BIT_3 0x00000008U
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#define BIT_4 0x00000010U
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#define BIT_5 0x00000020U
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#define BIT_6 0x00000040U
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#define BIT_7 0x00000080U
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#define BIT_8 0x00000100U
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#define BIT_9 0x00000200U
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#define BIT_10 0x00000400U
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#define BIT_11 0x00000800U
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#define BIT_12 0x00001000U
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#define BIT_13 0x00002000U
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#define BIT_14 0x00004000U
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#define BIT_15 0x00008000U
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#define BIT_16 0x00010000U
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#define BIT_17 0x00020000U
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#define BIT_18 0x00040000U
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#define BIT_19 0x00080000U
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#define BIT_20 0x00100000U
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#define BIT_21 0x00200000U
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#define BIT_22 0x00400000U
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#define BIT_23 0x00800000U
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#define BIT_24 0x01000000U
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#define BIT_25 0x02000000U
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#define BIT_26 0x04000000U
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#define BIT_27 0x08000000U
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#define BIT_28 0x10000000U
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#define BIT_29 0x20000000U
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#define BIT_30 0x40000000U
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#define BIT_31 0x80000000U
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#define SPEED_MASK 0x00000630U
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#define SPEED_10M 0x00000000U
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#define SPEED_100M 0x00000010U
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#define SPEED_1000M 0x00000020U
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#define SPEED_2500M 0x00000210U
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#define SPEED_5000M 0x00000220U
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#define SPEED_10000M 0x00000200U
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#define RTK_PHY_INTR_NEXT_PAGE_RECV (BIT_0)
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#define RTK_PHY_INTR_AN_COMPLETE (BIT_1)
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#define RTK_PHY_INTR_LINK_CHANGE (BIT_2)
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#define RTK_PHY_INTR_ALDPS_STATE_CHANGE (BIT_3)
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#define RTK_PHY_INTR_RLFD (BIT_4)
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#define RTK_PHY_INTR_TM_LOW (BIT_5)
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#define RTK_PHY_INTR_TM_HIGH (BIT_6)
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#define RTK_PHY_INTR_FATAL_ERROR (BIT_7)
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#define RTK_PHY_INTR_MACSEC (BIT_8)
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#define RTK_PHY_INTR_PTP1588 (BIT_9)
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#define RTK_PHY_INTR_WOL (BIT_10)
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#define RTL8261_MII_ADDR_C45 (1<<30)
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#define RTL8261_REG_ADDRESS(dev_ad, reg_num) (RTL8261_MII_ADDR_C45 |\
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((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF))
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#define RTL8261_MMD_PMAPMD 0x1
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#define RTL8261_MMD_PMAPMD_PHY_ID1 0x2
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#define RTL8261_MMD_PMAPMD_PHY_ID2 0x3
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#define RTL8261_MMD_AUTONEG 0x7
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#define RTL8261_MMD_AUTONEG 0x7
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#define RTL8261_MMD_AN_CTRL 0x0
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#define RTL8261_MMD_AN_STAT 0x1
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#define PHY_MMD_PCS 3
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#define PHY_MMD_AN 7
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#define PHY_MMD_VEND1 30 /* Vendor specific 1 */
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#define PHY_MMD_VEND2 31 /* Vendor specific 2 */
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#define REG32_FIELD_SET(_data, _val, _fOffset, _fMask) ((_data & ~(_fMask)) | ((_val << (_fOffset)) & (_fMask)))
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#define REG32_FIELD_GET(_data, _fOffset, _fMask) ((_data & (_fMask)) >> (_fOffset))
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#define UINT32_BITS_MASK(_mBit, _lBit) ((0xFFFFFFFF >> (31 - _mBit)) ^ ((1 << _lBit) - 1))
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#define RTK_PHYLIB_ERR_CHK(op)\
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do {\
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if ((ret = (op)) != 0)\
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{ \
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printf("error ret(%d) %s, %d\n", ret, __FUNCTION__, __LINE__); \
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return ret;\
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} \
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} while(0)
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typedef enum rtk_phypatch_type_e
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{
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PHY_PATCH_TYPE_NONE = 0,
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PHY_PATCH_TYPE_TOP = 1,
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PHY_PATCH_TYPE_SDS,
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PHY_PATCH_TYPE_AFE,
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PHY_PATCH_TYPE_UC,
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PHY_PATCH_TYPE_UC2,
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PHY_PATCH_TYPE_NCTL0,
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PHY_PATCH_TYPE_NCTL1,
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PHY_PATCH_TYPE_NCTL2,
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PHY_PATCH_TYPE_ALGXG,
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PHY_PATCH_TYPE_ALG1G,
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PHY_PATCH_TYPE_NORMAL,
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PHY_PATCH_TYPE_DATARAM,
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PHY_PATCH_TYPE_RTCT,
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PHY_PATCH_TYPE_END
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} rtk_phypatch_type_t;
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#define RTK_PATCH_TYPE_FLOW(_id) (PHY_PATCH_TYPE_END + _id)
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#define RTK_PATCH_TYPE_FLOWID_MAX PHY_PATCH_TYPE_END
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#define RTK_PATCH_SEQ_MAX ( PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX -1)
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#define uint8 u8
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#define uint16 u16
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#define uint32 u32
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#define int32 int32_t
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typedef struct rtk_hwpatch_s
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{
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uint8 patch_op;
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uint8 portmask;
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uint16 pagemmd;
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uint16 addr;
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uint8 msb;
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uint8 lsb;
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uint16 data;
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uint8 compare_op;
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uint16 sram_p;
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uint16 sram_rr;
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uint16 sram_rw;
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uint16 sram_a;
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} rtk_hwpatch_t;
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typedef struct rtk_hwpatch_data_s
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{
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rtk_hwpatch_t *conf;
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uint32 size;
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} rtk_hwpatch_data_t;
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typedef struct rtk_hwpatch_seq_s
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{
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uint8 patch_type;
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union
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{
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rtk_hwpatch_data_t data;
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uint8 flow_id;
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} patch;
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} rtk_hwpatch_seq_t;
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typedef struct rt_phy_patch_db_s
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{
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/* patch operation */
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int32_t (*fPatch_op)(u32 phy_id, u8 portOffset, rtk_hwpatch_t *pPatch_data, u8 patch_mode);
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int32_t (*fPatch_flow)(u32 phy_id, u8 portOffset, u8 patch_flow, u8 patch_mode);
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/* patch data */
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rtk_hwpatch_seq_t seq_table[RTK_PATCH_SEQ_MAX];
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rtk_hwpatch_seq_t cmp_table[RTK_PATCH_SEQ_MAX];
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} rt_phy_patch_db_t;
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int32_t phy_common_general_reg_mmd_get(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 *pData);
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int32_t phy_common_general_reg_mmd_set(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 data);
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int32_t rtk_phylib_time_usecs_get(ulong *pUsec);
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rt_phy_patch_db_t * get_patch_db(int32_t phy_id);
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#ifndef WAIT_COMPLETE_VAR
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#define WAIT_COMPLETE_VAR() \
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ulong _t, _now, _t_wait=0, _timeout; \
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int32 _chkCnt=0;
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#define WAIT_COMPLETE(_timeout_us) \
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_timeout = _timeout_us; \
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for(rtk_phylib_time_usecs_get(&_t),rtk_phylib_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \
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(_t_wait <= _timeout); \
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rtk_phylib_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \
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)
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#define WAIT_COMPLETE_IS_TIMEOUT() (_t_wait > _timeout)
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#endif
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#define HWP_PORT_SMI(phy_id) 0
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#define HWP_PHY_MODEL_BY_PORT(phy_id) 0
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#define HWP_PHY_ADDR(phy_id) 0
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#define HWP_PHY_BASE_MACID(phy_id) 0
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#define HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) if (bcast_phyad < 0x1F && p != NULL)
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#define RT_LOG(level, module, fmt, args...) do {} while(0)
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#define RT_ERR(error_code, module, fmt, args...) do {} while(0)
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#define RT_INIT_ERR(error_code, module, fmt, args...) do {} while(0)
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#define RT_INIT_MSG(fmt, args...) do {} while(0)
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#define phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad) 0
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#define PHYPATCH_DB_GET(phy_id, _pPatchDb) \
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do { \
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_pPatchDb = get_patch_db(phy_id); \
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/*printk("[PHYPATCH_DB_GET] ? [%s]\n", (_pDb != NULL) ? "E":"N");*/ \
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} while(0)
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#endif /* _RTL8261_PHY_H_ */
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